Emulator support mode for disabling and reconfiguring timeouts of a watchdog timer

• US 6,145,103 A
• Filed: 04/07/1998
• Issued: 11/07/2000
• Est. Priority Date: 04/07/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Typaldos, Melanie D., Maupin, Patrick E.
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US09/056,509
• Time in Patent Office: 945 Days
• Field of Search: 714/55, 714/56, 714/48, 714/25, 714/27, 714/28, 714/29, 714/30, 714/31, 714/35, 714/39, 714/45, 714/47, 364/282.8, 364/267.9, 395/575, 395/500.05, 395/500.44, 395/500.45, 395/500.49, 395/500.07
• US Class Current: 714/55
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key sequence to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its timeout value. By monitoring a condition as the watchdog timer approaches its timeout value, a software debugger may better predict and appreciate the behavior of a microcontroller-based device prior to a watchdog time-out. In a disclosed embodiment, the watchdog timer current count is readable and writable through a watchdog timer count high register and a watchdog timer count low register.

Claims

1. A watchdog timer having an emulator support mode for disabling watchdog time-outs, comprising:

a watchdog timer core;

a watchdog timer control register for controlling timing for the watchdog timer core; and

write enable logic for disabling writes to the watchdog timer control register in a normal operational mode subsequent to a write asserting an enable bit of the watchdog timer control register and enabling writes to the watchdog timer control register in the emulator support mode subsequent to a write asserting the enable bit.

2. The watchdog timer of claim 1, the write enable logic comprising:

key detect logic for asserting a global register signal provided to the watchdog timer control register in the emulator support mode responsive to detection of a write key and deasserting the global register signal and a flag register signal on the next access to the watchdog timer control register.

3. The watchdog timer of claim 1, further comprising:

emulator support mode detection logic for detecting the emulator support mode and providing an emulator support mode signal to the write enable logic when the emulator support mode is detected.

4. The watchdog timer of claim 1, further comprising:

count disable logic for deasserting the count enable signal to disable counting by the watchdog timer control register.

5. A watchdog timer having an emulator support for reconfiguring watchdog time-outs, comprising:

a watchdog timer core;

a watchdog timer current counter for indicating a current count of the watchdog timer core; and

current count logic for controlling the watchdog timer current counter, the current count logic being non-readable and non-programmable in a normal operational mode and being readable and programmable in an emulator support mode.

6. The watchdog timer of claim 5, the current count logic comprising:

a watchdog timer count low register readable and writable in the emulator support mode; and

a watchdog timer count high register readable and writable in the emulator support mode.

7. The watchdog timer of claim 5, further comprising:

emulator support mode detection logic for detecting the emulator support mode and providing an emulator support mode signal to the current count logic when the emulator support mode is detected.

8. A microcontroller having emulation support for disabling watchdog time-outs, comprising:

a microprocessor core;

a watchdog timer, comprising;

a watchdog timer control register controlling timing for the watchdog timer; and

write enable logic for disabling writes to the watchdog timer control register in a normal operational mode subsequent to a write asserting an enable bit of the watchdog timer control register and enabling writes to the watchdog timer control register subsequent to a write asserting the enable bit in the emulator support mode.

9. The microcontroller of claim 8, the write enable logic comprising:

key detect logic for asserting a global register signal to the watchdog timer control register in the emulator support mode responsive to detection of a write key and deasserting the global register signal on the next access to the watchdog timer control register.

10. The microcontroller of claim 8, the watchdog timer further comprising:

count disable logic for deasserting the count enable signal to disable counting by the watchdog timer control register.

11. The microcontroller of claim 8, the watchdog timer further comprising:

emulator support mode detection logic for detecting the emulator support mode and providing an emulator support mode signal to write enable logic when the emulator support mode is detected.

12. A microcontroller having emulator support for reconfiguring watchdog time-outs, comprising:

a microprocessor core;

a watchdog timer, comprising;

a watchdog timer current counter for indicating a current count of the watchdog timer; and

current count logic for controlling the watchdog timer current counter, the current count logic being non-readable and non-programmable in a normal operational mode and being readable and programmable in an emulator support mode.

13. The microcontroller of claim 12, the current count logic comprising:

a watchdog timer count low register readable and writable in the emulator support mode; and

a watchdog timer count high register readable and writable in the emulator support mode.

14. The microcontroller of claim 12, the watchdog timer further comprising:

emulator support mode detection logic for detecting the emulator support mode and providing an emulator support mode signal to the current count logic if the emulator support mode is detected.

15. The microcontroller of claim 14, further comprising:

emulator support mode triggering logic for triggering entry and exit for the emulator support mode.

16. The microcontroller of claim 15, the emulator support mode triggering logic comprising:

an emulator support mode bit for providing an emulator support mode signal to the emulator support mode detection logic.

17. The microcontroller of claim 15, wherein the emulator support mode triggering logic is only writable if an external pin of the microcontroller is pulled during a reset.

18. A method of decoupling the timing of a watchdog timer from code execution by an emulator, comprising the steps of:

detecting an indication to enter an emulator support mode of the watchdog timer; and

entering an emulator support mode for inhibiting the watchdog timer from counting.

19. The method of claim 18, the watchdog timer including a current count counter, the step of entering an emulator support mode comprising the step of:

deasserting a count enable signal to disable the current count counter from counting in the emulator support mode.

20. The method of claim 18, further comprising the steps of:

detecting an indication to exit the emulator support mode; and

exiting the emulator support mode to restart counting by the watchdog timer.

21. A method of reconfiguring a watchdog time-out of a watchdog timer, comprising the steps of:

placing the watchdog timer in an emulator support mode, a current count of the watchdog timer being programmable in the emulator support mode; and

programming the current count of the watchdog timer.

22. The method of claim 21, the watchdog timer including a watchdog timer count high register and a watchdog timer count low register, the step of programming the current count comprising the step of:

reading the watchdog timer count high register and the watchdog timer count low register.

23. The method of claim 21, the watchdog timer including a watchdog timer count high register and a watchdog timer count low register, the step of programming the current count comprising the step of:

writing to the watchdog timer count high register and the watchdog timer count low register.