Method for forming dynamic random access memory device with an ultra-short channel and an ultra-shallow junction

• US 6,146,955 A
• Filed: 11/12/1999
• Issued: 11/14/2000
• Est. Priority Date: 11/12/1999
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation, United Semiconductor Corp. (United Microelectronics Corporation)
• Inventors: Lee, Robin
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Kennedy, Jennifer M.
• Application Number:
  US09/439,791
• Time in Patent Office: 368 Days
• Field of Search: 438/291, 438/301, 438/303, 438/305
• US Class Current: 438/305
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A Method for forming a dynamic random access memory device with an ultra-short channel and an ultra-shallow junction is described in the invention. In the invention, the spacer is used as a mask to define the channel length of the device, so that the channel length of the device is not limited by the resolution of the photolithography process, and the performance of the device is improved thereby. Furthermore, an inversion layer serves as a junction to reduce the electric field; thus, the reliability of the device is increased.

Claims

1. A method for forming a dynamic random access memory device, comprising the following steps:

providing a substrate with an isolation structure;

forming a first oxide layer with a first opening exposing a first portion of the substrate on the substrate;

forming a pad oxide layer on the first portion of the substrate;

forming a first spacer on a sidewall of the first opening;

removing a portion of the pad oxide layer to expose a second portion of the substrate;

forming a gate oxide layer on the second portion of the substrate;

forming a first conductive layer within the first opening, wherein a surface of the first conductive layer is as high as that of the first oxide layer;

forming a silicide layer on the first conductive layer;

forming a second opening in the first oxide layer to expose a third portion of the substrate;

forming a second oxide layer on the third portion of the substrate;

forming a second spacer on a sidewall of the second opening;

removing a portion of the second oxide layer to form a first contact opening, wherein the first contact opening exposes the substrate;

forming a first doped region under the first contact opening in the substrate;

forming a second conductive layer within the first contact opening, wherein a surface of the second conductive layer is as high as that of the first oxide layer;

removing the first oxide layer and the first spacer;

performing an ion implantation process to form a second doped region and a third region in the substrate;

forming a first dielectric layer with a second contact opening exposing the second conductive layer over the substrate;

forming a bitline within the second contact opening, wherein the bitline couples with the first doped region via the second conductive layer;

forming a second dielectric layer over the substrate;

forming a storage node opening in the second dielectric layer and the first dielectric layer to expose the third doped region; and

forming a storage node within the storage node opening, wherein the storage node couples with the third doped region.

2. The method according to claim 1, wherein a material of the first spacer includes silicon nitride.

3. The method according to claim 1, wherein a material of the second spacer includes polysilicon.

4. The method according to claim 1, wherein a material of the bitline includes polysilicon.

5. The method according to claim 1, wherein the first conductive layer is preferably a wordline.

6. The method according to claim 1, wherein a material of the second conductive layer includes polysilicon.

7. The method according to claim 1, wherein a material of the storage node includes polysilicon.

8. The method according to claim 1, wherein the second oxide layer is thinner than the gate oxide layer.

9. A method for forming a device with an ultra-short channel, comprising the following steps:

forming a first oxide layer with a first opening on a substrate, wherein the first opening exposes the substrate;

forming a pad oxide layer in the first opening;

forming a first spacer on a sidewall of the first opening;

removing a portion of the pad oxide layer to expose the substrate;

forming a gate oxide layer in the first opening;

forming a first conductive layer within the first opening;

removing a portion of the first oxide layer to form a second opening exposing the substrate;

forming a second oxide layer in the second opening;

forming a second spacer on a sidewall of the second opening;

removing a portion of the second oxide layer to form a first contact opening exposing the substrate;

forming a source region under the first contact opening;

forming a second conductive layer within the first contact opening;

removing the first oxide layer and the first spacer; and

performing an ion implantation process to form a lightly doped drain region and a drain region in the substrate.

10. The method according to claim 9, wherein a material of the first spacer includes silicon nitride.

11. The method according to claim 9, wherein the material of the second spacer includes polysilicon.

12. The method according to claim 9, wherein the first conductive layer is preferably a wordline.

13. The method according to claim 9, wherein a material of the second conductive layer includes polysilicon.

14. The method according to claim 9, wherein the second oxide layer is thinner than the gate oxide layer.

15. The method according to claim 9, wherein a silicide layer is formed on the first conductive layer.