Creation of multiple gate oxide with high thickness ratio in flash memory process

• US 6,147,008 A
• Filed: 11/19/1999
• Issued: 11/14/2000
• Est. Priority Date: 11/19/1999
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Jin, Ying, Chwa, Siow Lee, Lin, Yung-Tao
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/443,421
• Time in Patent Office: 361 Days
• Field of Search: 438/981, 438/264, 438/762, 438/770
• US Class Current: 438/762
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A new method is provided for the creation of an oxide layer that contains three different thicknesses. A first layer of oxide is grown on the surface of a substrate; a first layer of photoresist is deposited and patterned thereby partially exposing the surface of the underlying first layer of oxide. A nitrogen implant is performed into the surface of the underlying substrate; the photoresist mask of the first layer of photoresist is removed. A second layer of photoresist is deposited and patterned, the first layer of oxide is removed from above and surrounding the implanted regions of the substrate. The second mask of resist is removed. The first layer of oxide is reduced in thickness, its thickness is restored to a first thickness by a blanket growth of a second layer of oxide over the exposed surface of the substrate (where no ion implant has been performed) to a third thickness, over the surface of the substrate where the ion implant has been performed to a second thickness and over the surface of the first layer of oxide thereby restoring this layer of oxide to its original first thickness.

Claims

1. A method of controlling gate oxide thickness in the fabrication of semiconductor devices, comprising the steps of:

providing a semiconductor substrate;

forming a layer of sacrificial oxide on the surface of said semiconductor substrate;

depositing a first layer over the surface of said layer of sacrificial oxide;

patterning and etching said first layer thereby creating an opening in said first layer said opening to extend to the surface of said layer of sacrificial oxide;

performing an ion implant into the surface of said semiconductor substrate whereby said ion implant aligns with said opening in said first layer;

removing said first layer from the surface of said layer of sacrificial oxide;

depositing a second layer over the surface of said layer of sacrificial oxide;

patterning and etching said second layer thereby creating an opening in said second layer said opening to include and expand beyond the area of said sacrificial oxide that overlies said ion implant;

removing said sacrificial oxide from the surface of said semiconductor substrate in accordance with said opening in said second layer thereby creating a patterned layer of sacrificial oxide thereby furthermore exposing the surface of said substrate underneath said opening;

removing said second layer from the surface of said layer of sacrificial oxide thereby exposing the surface of said patterned layer of sacrificial oxide;

reducing the thickness of said patterned layer of sacrificial oxide a measurable amount; and

blanket growing a second layer of oxide over said patterned layer of sacrificial oxide thereby including said exposed surface of said substrate.

2. The method of claim 1 wherein said semiconductor substrate is silicon.

3. The method of claim 1 wherein said depositing a first layer is depositing a layer of photoresist or passivation or dielectric or insulation to a thickness of about 10,000 Angstrom or any thickness that stops the implanting of particular ions into the surface of the substrate that is covered with said first layer.

4. The method of claim 1 wherein said depositing a second layer is depositing a layer of photoresist or a layer of passivation or a layer of dielectric or a layer of insulation.

5. The method of claim 1 wherein said performing an ion implant into the surface of said semiconductor substrate is implanting nitrogen ions at a dose of between about 10¹² and 10¹⁶ ions per cm² with an energy of between about 10 and 50 KeV.

6. The method of claim 1 with the additional step of annealing said sacrificial layer of oxide at a temperature between about 700 and 1200 degrees C. for a time between about 1 and 90 minutes said additional step to be performed after said step of forming a layer of sacrificial oxide.

7. The method of claim 1 wherein said gate oxide layer is thermally formed by subjecting the surface of said silicon substrate to oxidation in a dry O₂ environment at a temperature between about 700 to 1100 degrees C. for a time between about 4 and 25 minutes.

8. A method of controlling gate oxide thickness in the fabrication of semiconductor devices, comprising the steps of:

providing a silicon semiconductor substrate;

forming a layer of sacrificial oxide on the surface of said semiconductor substrate;

depositing a first layer over the surface of said layer of sacrificial oxide to a thickness of about 10,000 Angstrom or any thickness of said first layer that stops the implanting of particular ions into the surface of the substrate that is covered with said first layer;

patterning said first layer thereby creating an opening in said first layer said opening to extend to the surface of said layer of sacrificial oxide;

performing a nitrogen ion implant into the surface of said semiconductor with a dose of between about 10¹² and 10¹⁶ ions per cm² with an energy of between about 10 and 50 KeV into said substrate whereby said ion implant aligns with said opening in said first layer;

removing said first layer from the surface of said layer of sacrificial oxide;

depositing a second layer over the surface of said layer of sacrificial oxide;

patterning said second layer thereby removing said second layer from the surface of said sacrificial oxide over a measurable area said measurable area to include and expand beyond the area of said sacrificial oxide that overlies said ion implant;

removing said sacrificial oxide from the surface of said semiconductor substrate in accordance with said measurable area over which said second layer has been removed thereby creating a patterned layer of sacrificial oxide thereby furthermore exposing the surface of said substrate underneath said measurable area of said sacrificial oxide;

removing said second layer thereby exposing the surface of said patterned layer of sacrificial oxide;

reducing the thickness of said patterned layer of sacrificial oxide by a measurable amount; and

growing a second layer of oxide to a thickness of about 65 Angstrom over said patterned layer of sacrificial oxide thereby including said exposed surface of said substrate.

9. The method of claim 8 with the additional step of annealing said sacrificial layer of oxide at a temperature between about 700 and 1200 degrees C. for a time between about 1 and 90 minutes said additional step to be performed after said step of forming a layer of sacrificial oxide.

10. The method of claim 8 wherein said depositing a first layer is depositing a layer of photoresist or passivation or dielectric or insulation to a thickness of about 10,000 Angstrom or any suitable thickness that stops the implanting of particular ions into the surface of the substrate that is covered with said first layer.

11. The method of claim 8 wherein said depositing a second layer is depositing a layer of photoresist or a layer of passivation or a layer of dielectric or a layer of insulation.