Focal plane readout unit cell background suppression circuit and method

• US 6,147,340 A
• Filed: 09/29/1998
• Issued: 11/14/2000
• Est. Priority Date: 09/29/1998
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Levy, Miguel E.
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US09/163,937
• Time in Patent Office: 777 Days
• Field of Search: 250/214 R, 250/216, 250/208.1, 250/338.1, 250/370.08, 348/314, 348/308, 348/312, 348/295, 348/297
• US Class Current: 250/214.00R
• CPC Class Codes: H04N 25/575 with a response composed of multiple slopes

Abstract

A background suppression technique uses well-controlled and repeatable charge skimming operations to increase the charge capacities of the integration capacitors of integrated focal plane readout unit cells. A MOSFET (Q1) is connected to an integration capacitor (C_int) from which the quantity of stored charge is to be reduced. During each photocurrent integration period, the MOSFET is driven with a "skimming pulse" (V_sk) to draw charge from the capacitor. The skimming pulse is substantially shorter than an integration period, reducing the amount of noise contributed by the MOSFET'"'"'s noise mechanisms, and has an amplitude great enough to drive the MOSFET into its strong inversion mode, making the quantity of the removed charge relatively insensitive to variations in MOSFET threshold voltage. The charge skimming pulse is arranged to reduce the charge on the capacitor almost, but not quite, to zero, so that the entire integration period remains utilized.

Claims

1. A background suppression circuit suitable for use with a focal plane readout unit cell, comprising:

an integrating capacitor arranged to receive a first current for a predetermined integration period and to store the charge developed from said first current, said capacitor having a maximum charge capacity,

a transistor having a current circuit connected to said capacitor and a control input connected to receive a skimming pulse at least once per integration period, said transistor reducing the quantity of charge stored on said capacitor when said skimming pulse is received, and

a pulse generation circuit arranged to generate at least one of said skimming pulses per integration period, said at least one skimming pulse having a duration substantially shorter than said integration period and an amplitude sufficient to turn said transistor on,

said reduction of stored charge enabling an increased quantity of said first current to be integrated during said integration period when said first current would otherwise exceed the charge capacity of said capacitor.

2. The background suppression circuit of claim 1, wherein said transistor is a field-effect transistor (FET), said FET driven into its strong inversion mode when receiving said skimming pulse to reduce said suppression circuit'"'"'s sensitivity to threshold voltage manufacturing variations.

3. The background suppression circuit of claim 1, wherein said capacitor, transistor, and pulse generating circuit are integrated together on a common substrate.

4. A background suppression circuit suitable for use with an integrated focal plane readout unit cell, comprising:

an integrating capacitor arranged to receive a first current representing a photocurrent for a predetermined integration period and to store the charge developed from said first current, said capacitor having a maximum charge capacity,

a field-effect transistor (FET) having a current circuit connected to said capacitor and a control input connected to receive a skimming pulse at least once per integration period, said FET operating as a controlled current source which reduces the quantity of charge stored on said capacitor by a controlled amount when said skimming pulse is received, and

a pulse generation circuit arranged to generate at least one of said skimming pulses per integration period, said at least one skimming pulse having a duration substantially shorter than said integration period and an amplitude sufficient to drive said FET into its strong inversion mode, said capacitor, FET and pulse generation circuit integrated together on a common substrate,

said reduction of stored charge enabling an increased quantity of photocurrent to be integrated during said integration period when said photocurrent would otherwise exceed the charge capacity of said capacitor.

5. The background suppression circuit of claim 4, wherein said FET and said pulse generation circuit are arranged such that the quantity of charge stored on said capacitor is reduced to nearly zero when said FET receives said skimming pulse.

6. The background suppression circuit of claim 4, wherein said pulse generation circuit is arranged to generate said skimming pulse at about the middle of said integration period.

7. The background suppression circuit of claim 4, wherein said pulse generation circuit is arranged to generate said skimming pulse as the charge on said capacitor about reaches said maximum charge capacity.

8. The background suppression circuit of claim 4, wherein said pulse generation circuit is arranged to generate two or more skimming pulses per each integration period.

9. The background suppression circuit of claim 8, wherein said pulse generation circuit is arranged to generate a first skimming pulse after about 1/3 of said integration period has transpired and a second skimming pulse after about 2/3 of the integration period has transpired.

10. The background suppression circuit of claim 4, wherein said FET is arranged such that the gate voltage required to drive it into strong inversion is significantly higher than its threshold voltage to reduce said suppression circuit'"'"'s sensitivity to threshold voltage manufacturing variations.

11. The background suppression circuit of claim 4, further comprising a photodetector arranged to output a photocurrent from which said first current is derived.

12. The background suppression circuit of claim 11, further comprising a photodetector interface circuit connected to receive said photocurrent at an input and to produce said first current at an output.

13. The background suppression circuit of claim 12, wherein said photodetector interface circuit comprises a MOSFET connected in a common-gate configuration with its source connected to said photodetector and its drain connected to said integrating capacitor.

14. The background suppression circuit of claim 11, wherein said photodetector is an infrared-sensitive photodiode.

15. The background suppression circuit of claim 4, wherein said FET is a MOSFET arranged to sequentially reset said integrating capacitor to an initial state, remove a quantity of charge stored on said capacitor, and to readout the charge stored on said capacitor after said integration period has ended.

16. The background suppression circuit of claim 4, wherein said first current represents a photocurrent that includes a background component, said FET and said skimming pulse arranged to remove a quantity of charge from said capacitor nearly equal to the amount of charge developed from said background component.

17. The background suppression circuit of claim 4, wherein said integrating capacitor comprises a MOSFET configured as an inversion capacitor.

18. The background suppression circuit of claim 4, wherein said integrating capacitor comprises a MOS capacitor.

19. A focal plane readout unit cell with a background suppression circuit, comprising:

a photodetector interface circuit connected to receive a photocurrent at an input and to produce a first current at an output,

an integrating capacitor arranged to receive said first current for a predetermined integration period and to store the charge developed from said first current, said capacitor having a maximum charge capacity,

a field-effect transistor (FET) having a current circuit connected to said capacitor and a control input connected to receive a skimming pulse, said FET operating as a controlled current source which reduces the quantity of charge stored on said capacitor by a controlled amount when said skimming pulse is received, and

a pulse generation circuit arranged to generate at least one of said skimming pulses per integration period, said at least one skimming pulse having a duration substantially shorter than said integration period and an amplitude sufficient to drive said FET into its strong inversion mode, said photodetector interface circuit, integrating capacitor, FET and pulse generation circuit integrated together on a common substrate,

said reduction of stored charge enabling an increased quantity of photocurrent to be integrated during said integration period when said photocurrent would otherwise exceed the charge capacity of said integrating capacitor.

20. The focal plane readout unit cell of claim 19, further comprising a photodetector arranged to output said photocurrent to said photodetector interface circuit.

21. The focal plane readout unit cell of claim 19, wherein said photocurrent includes a background component and said FET and said skimming pulse are arranged to remove a quantity of charge from said integrating capacitor nearly equal to the amount of charge developed from said background component.

22. An integrated focal plane array with improved background suppression, comprising:

a plurality of focal plane readout unit cells arranged into a row and column array, each unit cell comprising;

a photodetector interface circuit connected to receive a photocurrent at an input and to produce a first current at an output,

an integrating capacitor arranged to receive said first current for a predetermined integration period and to store the charge developed from said first current, said capacitor having a maximum charge capacity, and

a field-effect transistor (FET) having a current circuit connected to said capacitor and a control input connected to receive a skimming pulse, said FET operating as a controlled current source which reduces the quantity of charge stored on said capacitor by a controlled amount when said skimming pulse is received;

clock generation circuitry arranged to generate at least one of said skimming pulses per integration period for each of said FETs in said array, each skimming pulse having a duration substantially shorter than said integration period and an amplitude sufficient to drive the receiving FET into its strong inversion mode, and

a plurality of column multiplexers connected to respective columns of said unit cells for assembling the charges from said array of unit cells into a video frame, said unit cells, clock generation circuitry and column multiplexers integrated together on a common substrate.

23. The focal plane array of claim 22, further comprising a plurality of photodetectors connected to respective focal plane readout unit cells and supplying said photocurrents to said photodetector interface circuits.

24. The focal plane array of claim 23, wherein said photodetectors are infrared-sensitive photodiodes.

25. The focal plane array of claim 22, wherein each of said unit cells'"'"' respective FETs is a MOSFET arranged to sequentially reset its unit cell'"'"'s integrating capacitor to an initial state, remove charge from its unit cell'"'"'s capacitor during said integration period, and to readout the charge stored on its unit cell'"'"'s capacitor after said integration period has ended.

26. A method of removing charge from the integrating capacitor of a focal plane readout unit cell to allow said capacitor to accommodate a higher maximum photocurrent, comprising the steps of:

integrating a photocurrent on an integrating capacitor over an integration period, said integrating capacitor having a maximum charge capacity, and

drawing current from said capacitor during said integration period to reduce the quantity of charge stored on said capacitor, said current drawn from said capacitor for a period substantially shorter than said integration period, said charge reduction enabling an increased quantity of photocurrent to be integrated during said integration period when said photocurrent would otherwise exceed the charge capacity of said capacitor.

27. The method of claim 26, further comprising the step of applying at least one pulse per integration period to the control input of a transistor having its current circuit connected between said capacitor and a current sink, said transistor operating as a controlled current source, said pulse causing said transistor to turn on and draw current from said capacitor to said current sink.

28. The method of claim 27, wherein said transistor is a MOSFET and said pulse causes said MOSFET to be driven into its strong inversion mode such that the quantity of stored charge removed by said MOSFET is relatively insensitive to variations in said MOSFET'"'"'s threshold voltage.

29. The method of claim 27, wherein said at least one pulse is a single pulse applied to the control input of said transistor at about the middle of said integration period.

30. The method of claim 27, wherein said photocurrent includes a background component, said transistor and said skimming pulse arranged to remove a quantity of charge from said capacitor nearly equal to the amount of charge developed from said background component.