Wafer test fixture using a biasing bladder and methodology

• US 6,147,506 A
• Filed: 04/29/1997
• Issued: 11/14/2000
• Est. Priority Date: 04/29/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ahmad, Umar M. U., Atwood, Eugene R.
• Primary Examiner(s): Snow, Walter E.
• Application Number:
  US08/841,012
• Time in Patent Office: 1,295 Days
• Field of Search: 324/760, 324/754, 324/755, 324/758, 324/765, 324/158.1
• US Class Current: 324/750.05
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801

Abstract

A wafer test and burn-in fixture and methodology including a wafer probe having flexible tabs and a load board coupled to the wafer probe using the flexible tabs. The fixture also includes a bladder which biases the wafer probe to contact a wafer. A temperature control apparatus is provided to control the temperature of the wafer probe and the wafer. Tests are performed on the wafer using built-in self tests or wrap wiring tests.

Claims

1. A test apparatus for testing a wafer comprising:

a wafer probe of a material with substantially the same thermal expansion characteristics as the wafer being tested, the wafer probe including a plurality of flexible tabs of a flat shape and positioned generally horizontally between the load board and the wafer probe;

a load board coupled to the wafer probe by the flexible tabs;

a bladder for biasing the wafer probe; and

testing means for testing the wafer using a reduced pin test methodology.

2. The test apparatus according to claim 1 wherein the testing means is further for testing the wafer during burn-in.

3. The test apparatus according to claim 1 further comprising temperature control means for controlling the temperature of the wafer probe and the wafer.

4. The test apparatus according to claim 3 wherein the temperature control means increases, decreases or maintains the temperature of the wafer probe and the wafer.

5. The test apparatus according to claim 1 wherein the wafer includes at least one die having input/output (I/O) ports and the wafer probe further comprises wrap wiring for interconnecting one I/O port of the die with another I/O port of the die.

6. The test apparatus according to claim 1 wherein the wafer has a plurality of dice and the wafer probe comprises a plurality of die test sites, each one of the plurality of die test sites corresponding to one of the plurality of dice.

7. The test apparatus according to claim 1 wherein the wafer probe comprises a plurality of die test sites, each one of the plurality of die test sites having at least one of a power source, a decoupling capacitor, and over current sense and control circuitry.

8. The test apparatus according to claim 7 wherein the power source is a field effect transistor.

9. The test apparatus according to claim 7 wherein the over current sense and control circuitry shuts down the power source if a current to a die on the wafer exceeds a threshold.

10. The test apparatus according to claim 7 wherein each one of the plurality of die test sites includes a power source and a decoupling capacitor.

11. The test apparatus according to claim 10 wherein the wafer includes at least one die having I/O ports and each one of the plurality of die test sites further includes wrap wiring for interconnecting one I/O port of the die with another I/O port of the die.

12. The test apparatus according to claim 10 wherein the power source is a field effect transistor.

13. The test apparatus according to claim 1 wherein the testing means includes means for testing the wafer using a reduced pin test methodology.

14. The test apparatus according to claim 1 wherein the test methodology includes at least one of an LSSD test, a built-in self test, and a wrap wiring test.

15. The test apparatus according to claim 1 further comprising means for holding the wafer probe and the wafer in alignment.

33. The test apparatus according to claim 1, wherein the flexible tabs are flexible to the extent to permit the wafer probe to move in a generally vertical direction relative to the load board.

34. The test apparatus according to claim 1, wherein each flexible tab includes at least one of a bump array, contact array, and intersection lines for providing an electrical connection between the load board and the wafer probe.

35. The test apparatus according to claim 1, wherein each flexible tab has fan out signal connectors extending therefrom for electrical connection with the load board and thereby each flexible tab provides for misalignment between the load board and the wafer probe.

16. A test apparatus for testing a wafer comprising:

a wafer probe including flexible tabs, the wafer probe of a material with substantially the same thermal expansion characteristics as the wafer being tested;

a load board coupled to the wafer probe using the flexible tabs of a generally flat shape to be positioned horizontally between the load board and the wafer probe;

a bladder which biases the wafer probe to contact the wafer; and

temperature control means for controlling the temperature of the wafer probe and the wafer.

17. The test apparatus according to claim 16 further comprising testing means for testing the wafer using at least one of a built-in self test and a wrap wiring test.

18. The test apparatus according to claim 16 wherein the temperature control means increases the temperature of the wafer probe and the wafer.

19. The test apparatus according to claim 16 wherein the wafer includes at least one die having input/output (I/O) ports and the wafer probe further comprises wrap wiring for interconnecting one I/O port of the die with another I/O port of the die.

20. The test apparatus according to claim 16 wherein the wafer has a plurality of dice and the wafer probe comprises a plurality of die test sites, each one of the plurality of die test sites corresponding to one of the dice.

21. The test apparatus according to claim 16 wherein the wafer probe comprises a plurality of die test sites, each one of the plurality of die test sites having at least one of a power source, a decoupling capacitor, and over current sense and control circuitry.

22. The test apparatus according to claim 21 wherein the over current sense and control circuitry shuts down the power source if a current to a die on the wafer exceeds a threshold.

23. The test apparatus according to claim 21 wherein each one of the plurality of die test sites includes a power source and a decoupling capacitor.

24. The test apparatus according to claim 21 wherein the power source is a field effect transistor.

25. The test apparatus according to claim 21 wherein the wafer includes at least one die having I/O ports and each one of the plurality of die test sites further includes wrap wiring for interconnecting one I/O port of the die with another I/O port of the die.

26. The test apparatus according to claim 16 wherein the testing means includes means for testing the wafer using a reduced pin test methodology.

32. The method according to claim 20 further comprising the steps of:

providing a load board and flexible tabs; and

coupling the load board to the wafer probe using the flexible tabs.

36. The test apparatus according to claim 16, wherein each flexible tab has fan out signal connectors extending therefrom for electrical connection with the load board and thereby each flexible tab provides for misalignment between the load board and the wafer probe.

27. A method for testing a wafer comprising the steps of:

(a) providing a wafer probe which is of a material with substantially the same thermal expansion characteristics as the wafer being tested, the wafer probe including a plurality of flexible tabs for coupling the wafer probe to a load board, the flexible tabs being of a generally flat shape and positioned generally horizontally between the load board and the wafer probe;

(b) biasing the wafer probe to contact the wafer; and

(c) testing the wafer using at least one of a built-in self test and a warp wiring test.

28. The method according to claim 27 wherein step (c) further comprises the step of testing the wafer during burn-in.

29. The method according to claim 27 further comprising the step of (d) controlling the temperature of the wafer probe and the wafer.

30. The method according to claim 29 wherein step (d) includes the step of increasing the temperature of the wafer probe and the wafer.

31. The method according to claim 27 wherein the wafer probe provided in step (a) further comprises a plurality of die test sites, each one of the plurality of die test sites having at least one of a power source, a decoupling capacitor, and over current sense and control circuitry.

37. The method according to claim 27 wherein each flexible tab has fan out signal connectors extending therefrom for electrical connection with the load board and thereby each flexible tab provides for misalignment between the load board and the wafer probe.