Overvoltage-tolerant interface for integrated circuits

• US 6,147,511 A
• Filed: 05/27/1997
• Issued: 11/14/2000
• Est. Priority Date: 05/28/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wong, Wilson, Patel, Rakesh H., Turner, John E.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/863,886
• Time in Patent Office: 1,267 Days
• Field of Search: 326/80-81, 326/83, 326/86, 326/121
• US Class Current: 326/81
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018585 programmable

Abstract

An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an "overvoltage condition. " For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.

Claims

1. A circuit to implement an overvoltage-tolerant integrated circuit comprising:

a pull-up device coupled between a first supply voltage and an I/O pad; and

a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising;

a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;

a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;

a first clamping device coupled between the first supply voltage and a first node, not directly connected to the voltage bias node;

a second clamping device coupled between the I/O pad and the first node; and

a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.

2. The circuit of claim 1 wherein a second body electrode of the first bias device and a third body electrode of the second bias device are coupled to the voltage bias node.

3. The circuit of claim 1 wherein the body bias generator further comprises:

a voltage clamp circuit coupled to clamp the voltage bias node to a voltage at or above about a level of the first supply voltage.

4. The circuit of claim 1 further comprising:

a predriver to drive the pull-up device; and

an isolation device between the predriver and the control electrode of the pull-up device.

5. The circuit of claim 1 further comprising:

a resistive device coupled between the I/O pad and the first bias device and between the I/O pad and the second bias device.

6. The circuit of claim 1 further comprising:

an input buffer comprising a thick oxide transistor with a control electrode coupled to receive a signal at the I/O pad.

7. The circuit of claim 1 wherein the first bias device and second bias device are thick oxide transistors.

8. The circuit of claim 1 wherein the voltage bias node is coupled to body electrodes of the first bias device, second bias device, third bias device, first clamping device, and second clamping device.

9. An integrated circuit comprising:

a pull-up device coupled between a first supply voltage and an I/O pad; and

a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising;

a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;

a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;

a first clamping device coupled between the first supply voltage and a first node;

a second clamping device coupled between the I/O pad and the first node;

a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state; and

a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad.

10. A circuit to implement an overvoltage-tolerant integrated circuit comprising:

a pull-up device coupled between a first supply voltage and an I/O pad; and

a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising;

a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;

a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; and

;

a third bias device to couple the voltage bias node to a control electrode of the pull-up device whenever the pull-up device is in a nonconducting state.

11. The circuit of claim 10 wherein a second body electrode of the first bias device and a third body electrode of the second bias device are coupled to the voltage bias node.

12. The circuit of claim 10 wherein the body bias generator further comprises:

a voltage clamp circuit coupled to clamp the voltage bias node to a voltage at or above about a level of the first supply voltage.

13. The circuit of claim 10 wherein the body bias generator further comprises:

a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad.

14. The circuit of claim 10 further comprising:

a predriver to drive the pull-up device; and

an isolation device between the predriver and the control electrode of the pull-up device.

15. The circuit of claim 10 further comprising:

a resistive device coupled between the I/O pad and the first bias device and between the I/O pad and the second bias device.

16. The circuit of claim 10 further comprising:

an input buffer comprising a thick oxide transistor with a control electrode coupled to receive a signal at the I/O pad.

17. The circuit of claim 14 wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage.

18. The circuit of claim 10 wherein the first bias device and second bias device are thick oxide transistors.

19. The circuit of claim 10 wherein the voltage bias node is coupled to body electrodes of the first bias device, second bias device, and third bias device.

20. The circuit of claim 10 further comprising:

a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage.

21. The circuit of claim 20 wherein a body electrode of the first pass device is coupled to the voltage bias node.

22. The circuit of claim 20 further comprising:

a second pass device coupled between a predriver output node and the control electrode of the pull-up device, wherein a control electrode of the second pass device is coupled to the I/O pad.

23. The circuit of claim 20 wherein a body electrode of the second pass device is coupled to the voltage bias node.

24. An intergrated circuit comprising:

a pull-up device coupled between a first supply voltage and an I/O pad;

a predriver to drive the pull-up device; and

an isolation device between the predriver and the control electrode of the pull-up device, wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage; and

a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising;

a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;

a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;

a first clamping device coupled between the first supply voltage and a first node;

a second clamping device coupled between the I/O pad and the first node; and

a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.

25. An integrated circuit comprising:

a pull-up device coupled between a first supply voltage and an I/O pad;

a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage; and

a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising;

a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;

a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;

a first clamping device coupled between the first supply voltage and a first node;

a second clamping device coupled between the I/O pad and the first node; and

a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.

26. The circuit of claim 25 wherein a body electrode of the first pass device is coupled to the voltage bias node.

27. The circuit of claim 25 further comprising:

a second pass device coupled between a predriver output node and the control electrode of the pull-up device, wherein a control electrode of the second pass device is coupled to the I/O pad.

28. The circuit of claim 25 wherein a body electrode of the second pass device is coupled to the voltage bias node.

29. A circuit to implement an overvoltage-tolerant integrated circuit comprising:

a pull-up device coupled between a first supply voltage and an I/O pad;

a predriver to drive the pull-up device; and

an isolation device between the predriver and the control electrode of the pull-up device, wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage, and

a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising;

a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; and

a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage, wherein the first bias device and the second bias device have a first gate oxide thickness that is thicker than a second gate oxide thickness of transistors used to implement the predriver.

30. The circuit of claim 29 wherein the isolation device has the first gate oxide thickness.

31. The circuit of claim 29 wherein a second body electrode of the first bias device and a third body electrode of the second bias device are coupled to the voltage bias node.

32. The circuit of claim 29 wherein the body bias generator further comprises:

a voltage clamp circuit coupled to clamp the voltage bias node to a voltage at or above about a level of the first supply voltage.

33. The circuit of claim 32 wherein the voltage clamp circuit has the first gate oxide thickness.

34. The circuit of claim 29 wherein the body bias generator further comprises:

a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad.

35. The circuit of claim 34 wherein the voltage clamp device has the first gate oxide thickness.

36. The circuit of claim 29 wherein the body bias generator further comprises:

a third bias device to couple the voltage bias node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.

37. The circuit of claim 36 wherein the third bias device has the first gate oxide thickness.

38. The circuit of claim 29 further comprising:

a resistive device coupled between the I/O pad and the first bias device and between the I/O pad and the second bias device.

39. The circuit of claim 29 further comprising:

an input buffer comprising a transistor with the first oxide thickness and a control electrode coupled to receive a signal at the I/O pad.

40. The circuit of claim 29 wherein the body bias generator further comprises:

a first clamping device coupled between the first voltage source and a first node;

a second clamping device coupled between the I/O pad and the first node; and

a third bias device to couple the first node to the control electrode of the pull-up device when the pull-up device is in a nonconducting state.

41. The circuit of claim 40 wherein the first clamping device and third bias device have the first gate oxide thickness.

42. The circuit of claim 41 wherein the voltage bias node is coupled to body electrodes of the first bias device, second bias device, third bias device, first clamping device, and second clamping device.

43. The circuit of claim 29 wherein the pull-up device has the first gate oxide thickness.

44. The circuit of claim 29 further comprising:

a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage.

45. The circuit of claim 44 wherein a body electrode of the first pass device is coupled to the voltage bias node.

46. The circuit of claim 44 further comprising:

a second pass device coupled between a predriver output node and the control electrode of the pull-up device, wherein a control electrode of the second pass device is coupled to the I/O pad.

47. The circuit of claim 44 wherein a body electrode of the second pass device is coupled to the voltage bias node.

48. A circuit to implement an overvoltage-tolerant integrated circuit comprising:

a pull-up device coupled between a first supply voltage and an I/O pad;

a predriver to drive a control electrode of the pull-up device with a pull-up signal; and

a body bias generator, having a voltage bias node coupled to a first body electrode of the pull-up device, comprising;

a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;

a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; and

a third bias device, coupled between the voltage bias node and the control electrode of the pull-up device, wherein a control electrode of the third bias device is coupled to an inverted version of the pull-up signal.

49. The circuit of claim 48 further comprising:

an isolation device coupled between the predriver and the control electrode of the pull-up device.

50. The circuit of claim 48 wherein the body bias generator further comprises:

a voltage clamp circuit coupled to clamp the voltage bias node to a voltage at or above about a level of the first supply voltage.

51. The circuit of claim 48 wherein the body bias generator further comprises:

a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad.

52. The circuit of claim 48 further comprising:

a resistive device coupled between the I/O pad and the first bias device and between the I/O pad and the second bias device.

53. The circuit of claim 48 further comprising:

an input buffer comprising a thick oxide transistor with a control electrode coupled to receive a signal at the I/O pad.

54. The circuit of claim 49 wherein the isolation device has a control electrode coupled to the first supply voltage.

55. The circuit of claim 48 wherein the first bias device and second bias device are thick oxide transistors.

56. The circuit of claim 48 wherein the voltage bias node is coupled to body electrodes of the first bias device, second bias device, and third bias device.

57. The circuit of claim 48 further comprising:

a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage.

58. The circuit of claim 57 wherein a body electrode of the first pass device is coupled to the voltage bias node.

59. The circuit of claim 57 further comprising:

a second pass device coupled between a predriver output node and the control electrode of the pull-up device, wherein a control electrode of the second pass device is coupled to the I/O pad.

60. The circuit of claim 57 wherein a body electrode of the second pass device is coupled to the voltage bias node.