Sense amplifier circuit

• US 6,147,514 A
• Filed: 12/09/1998
• Issued: 11/14/2000
• Est. Priority Date: 12/11/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shiratake, Shinichiro
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/208,187
• Time in Patent Office: 706 Days
• Field of Search: 327/51-57, 327/333, 365/205, 365/207, 365/208
• US Class Current: 327/55
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

This invention provides a sense amplifier circuit capable of determining an output with small power consumption at high speeds and simplifying a control signal. The sources of a pair of driver nMOS transistors in a first amplifier are connected to VSS via an activation nMOS transistor. An output from the first amplifier is directly input to input/output nodes of a second, latch amplifier. The sources of a pair of nMOS transistors in the second amplifier are connected to VSS via an activation nMOS transistor. The input/output nodes are precharged to VCC by a precharge circuit in a standby state. The activation nMOS transistors are simultaneously controlled by a clock signal, and the first and second amplifiers are simultaneously activated to sense, amplify, and latch the potential difference between input/output nodes.

Claims

1. A sense amplifier circuit comprising:

first and second input terminals;

a voltage source terminal connected to a voltage source;

a reference potential terminal connected to a reference potential;

a clock signal terminal for receiving a clock signal;

a first amplifier electrically connected to the first and second input terminals and the voltage source terminal, for sensing a potential difference between the input terminals and outputting differential outputs;

a first activation circuit connected to the clock signal terminal, the first amplifier, and the reference voltage terminal, for activating the first amplifier in accordance with the clock signal;

a second amplifier of latch-type connected to the voltage source terminal, having first and second input/output nodes respectively connected to the differential outputs from the first amplifier, for amplifying the differential output from said first amplifier and latching the amplified differential outputs;

first and second output terminals respectively connected to the first and second input/output nodes, for extracting output signals therefrom;

a second activation circuit connected to the second amplifier, for activating the second amplifier in association with said first amplifier; and

switching elements arranged on paths of current flowing from the input/out nodes to the reference potential terminal through said first amplifier, for interrupting the current flow on the paths.

2. The circuit according to claim 1, further comprising an OR gate receiving signals from said first and second output terminals and a NOR gate receiving an output signal from said OR gate and said clock signal, wherein both of said first activation circuit and said switching elements are comprised of the same pair of MOS transistors, and gates of said pair of MOS transistors are connected to an output of said NOR gate.

3. The circuit according to claim 1,

wherein each of said switching elements comprises a switching MOS transistor, said circuit further comprising buffer circuits each having an input terminal connected to one of said two output terminals and an output terminal connected to a gate of the switching MOS transistor.

4. The circuit according to claim 1, wherein:

said first activation circuit comprises first and second activating MOS transistors, drains of said first and second activating MOS transistors being connected to said first amplifier and said reference potential terminal, said first and second switching MOS transistors being respectively inserted between said reference potential terminal and said first and second activating MOS transistors to be connected in series thereto.

5. The circuit according to claim 1, wherein said switching elements each comprise a switching MOS transistor having a gate connected to a corresponding one of said input/output terminals, said switching MOS transistor inserted between the other of said input/output terminals and said second activation circuit.

6. The circuit according to claim 5, further comprising a clock signal terminal receiving a clock signal and a precharge circuit for setting the two input/output nodes at a predetermined potential prior to activation of said first and second amplifiers in accordance with said clock signal.

7. A circuit according to claim 5, wherein said second amplifier comprises a load used in common with said first amplifiers.

8. A circuit according to claim 5, further comprising one or more delay elements connected to said second activation circuit and said first activation circuit, for turning said second activation circuit on with a delay with respect to said first activation circuit.

9. A sense amplifier circuit comprising:

first and second input terminals;

a voltage source terminal connected to a voltage source;

a reference potential terminal connected to a reference potential;

a clock signal terminal receiving a clock signal;

a first amplifier having first and second current paths respectively connected to the first and second input terminals, the voltage source terminal and the reference potential terminal, for sensing a potential difference between said two input terminals and for outputting differential outputs;

a first activation circuit connected to the clock signal terminal and the first amplifier, for activating the first amplifier in accordance with the clock signal;

a second amplifier of latch-type, having first and second input/output nodes respectively connected to the voltage source terminal, the reference potential terminal, and the first and second current paths, for amplifying differential outputs from said first amplifier and latching the amplified differential outputs;

first and second output terminals respectively connected to the first and second input/output nodes of the second amplifier, for extracting output signals;

first and second buffer circuits respectively connected to said first and second output terminals;

a second activation circuit comprising first and second MOS transistors connected in series to each other, wherein the ends of the MOS transistors respectively are connected to the first and second current paths, the node between the MOS transistors are connected to said second amplifier, gates of the first and second MOS amplifiers respectively are connected to the second and first buffer circuits;

switching elements comprising first and second MOS transistors arranged on the first and second current paths, the gates of which are respectively connected to the second and first buffer circuits; and

a precharge circuit connected to the voltage source terminal and the first and second input/output nodes, for setting the two input/output nodes at a predetermined potential prior to activation of said first and second amplifiers in accordance with the clock signal.

10. The circuit according to claim 9, wherein:

said first amplifier comprises;

a first activation node and

a first channel having first and second drive MOS transistors having sources commonly connected to said first activation node and having drains respectively connected to the two input/output nodes,

said first activation circuit comprises an activating MOS transistor being arranged and connected between said first activation node and the reference voltage, and having a gate connected to said clock signal terminal,

said second amplifier comprises;

a second activation node;

a second channel having first and second MOS transistors which have sources being connected in common to said second activation node, drains being connected to said input/output nodes, and gates being connected to said second and first input/output nodes, respectively; and

a third channel having third and fourth MOS transistors which have sources being connected in common to said voltage source terminal, drains being connected to said two input/output nodes, and gates being connected to said second and first input/output nodes, respectively, and

the third and fourth MOS transistors of the third channel of said second amplifier are used as the load MOS transistors for said first amplifier.

11. A circuit according to claim 10, wherein:

said precharge circuit are connected to said voltage source terminal and said first and second input/output nodes, said precharge circuit comprises first and second precharge MOS transistors the gates of which are connected in common to said clock signal terminal, and a short-circuiting MOS transistor are inserted between the first and second current paths for short-circuiting the first and second current paths, the gate of which is connected to said clock signal terminal.

12. A sense amplifier circuit comprising:

first and second input terminals;

a voltage source terminal connected to a voltage source;

a reference potential terminal connected to a reference potential;

a clock signal terminal for receiving a clock signal;

a first amplifier electrically connected to the input terminals and the voltage source terminal, for sensing a potential difference between the input terminals and outputting differential outputs;

a first activation circuit connected to the clock signal terminal, the first amplifier, and the reference voltage terminal for activating the first amplifier in accordance with the clock signal;

a second amplifier of latch-type connected to the voltage source terminal, having first and second input/output nodes respectively connected to the differential outputs from the first amplifier, for amplifying the differential outputs from said first amplifier and latching the amplified differential outputs;

first and second output terminals respectively connected to the first and second input/output nodes of the second amplifier, for extracting output signals therefrom; and

a second activation circuit connected to the clock signal terminal and the second amplifier, for activating the second amplifier in accordance with the clock signal,

wherein said first activation circuit has a first activation node, and said second activation circuit has a second activation node, said first activation circuit connects the first activation node to the reference potential when it is activated, and said second activation circuit connects the second activation node to the reference potential via the first activation node connected to the reference potential when said first activation circuit is turned on.

13. A sense amplifier circuit comprising:

first and second input terminals;

a voltage source terminal connected to a voltage source;

a reference potential terminal connected to a reference potential;

a clock signal terminal for receiving a clock signal;

a first amplifier electrically connected to the input terminals and the voltage source terminal, for sensing a potential difference between the input terminals and outputting differential outputs;

a first activation circuit connected to the clock signal terminal, the first amplifier, and the reference voltage terminal for activating the first amplifier in accordance with the clock signal;

a second amplifier of latch-type connected to the voltage source terminal, having first and second input/output nodes respectively connected to the differential outputs from the first amplifier, for amplifying the differential outputs from said first amplifier and latching the amplified differential outputs;

first and second output terminals respectively connected to the first and second input/output nodes of the second amplifier, for extracting output signals therefrom;

a second activation circuit connected to the clock signal terminal and the second amplifier, for activating the second amplifier in accordance with the clock signal; and

one or more delay elements inserted between said second activation circuit and said clock signal terminal, for turning said second activation circuit on with a delay in conjunction with said first activation circuit.

14. A sense amplifier circuit comprising:

first and second input terminals;

a voltage source terminal connected to a voltage source;

a reference potential terminal connected to a reference potential;

a clock signal terminal for receiving a clock signal;

a first amplifier electrically connected to the input terminals and the voltage source terminal, for sensing a potential difference between the input terminals and outputting differential outputs;

a first activation circuit connected to the clock signal terminal, the first amplifier, and the reference voltage terminal for activating the first amplifier in accordance with the clock signal;

a second amplifier of latch-type connected to the voltage source terminal, having first and second input/output nodes respectively connected to the differential outputs from the first amplifier, for amplifying the differential outputs from said first amplifier and latching the amplified differential outputs;

first and second output terminals respectively connected to the first and second input/output nodes of the second amplifier, for extracting output signals therefrom;

a second activation circuit connected to the clock signal terminal and the second amplifier, for activating the second amplifier in accordance with the clock signal,

wherein;

said first amplifier comprises;

a first activation node; and

a first channel having first and second driver MOS transistors having sources connected in common to said first activation node, and having drains respectively connected to the first and second input/output nodes,

said first activation circuit comprises an activating MOS transistor being inserted between said first activation node and the reference voltage terminal, and having a gate connected to said clock signal terminal,

said second amplifier comprises;

a second activation node;

a second channel having third and fourth MOS transistors which have sources being connected in common to said second activation node, drains being connected to said first and second input/output nodes, and gates being connected to said second and first input/output nodes, respectively; and

a third channel having fifth and sixth MOS transistors which have sources being connected in common to said voltage source terminal, drains being connected to said first and second input/output nodes, and gates being connected to said second and first input/output nodes, respectively,

said second activation circuit comprises an activation MOS transistor being arranged and connected between said second activation node and the reference voltage terminal, and having a gate connected to said clock signal terminal, and

the fifth and sixth MOS transistors of the third channel in said second amplifier are used as the load MOS transistors for said first amplifier.