Charge pump circuit capable of generating positive and negative voltages and nonvolatile semiconductor memory device comprising the same

• US 6,147,547 A
• Filed: 10/15/1998
• Issued: 11/14/2000
• Est. Priority Date: 05/25/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ogura, Taku, Mihara, Masaaki
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/172,769
• Time in Patent Office: 761 Days
• Field of Search: 327/536, 327/589, 327/534, 327/535, 327/537, 327/390, 326/88
• US Class Current: 327/536
• CPC Class Codes: H02M 1/009 having two or more independently controlled outputs for DC-DC converter with intermediate AC H02M3/33561
• CPC Class Codes: H02M 3/071 adapted to generate a negative voltage output from a positive voltage source
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

Output nodes (Noutn, Noutp) outputting a negative potential (VN) and a positive potential (VPS) respectively are supplied with fixed potentials by reset circuits respectively when unused. Switches (SW2, SW3) conduct when generating the negative potential, while switches (SW1, SW4) conduct when generating the positive potential. Reference potentials for the generated potentials are supplied to internal nodes (N10, N20) through the switches (SW1, SW3) respectively. Poly-diode elements are employed for a voltage generation part, whereby a charge pump circuit capable of generating positive and negative voltages can be implemented without remarkably changing a fabrication method.

Claims

1. A charge pump circuit provided on a semiconductor substrate, comprising:

a first power supply node receiving a first power supply potential;

a second power supply node receiving a second power supply potential being lower than said first power supply potential;

a pumping portion having a first and a second internal nodes, driven by a clock signal and rendering the potential of said second internal node higher than that of a first internal node;

said pumping portion including;

a first poly-diode element so provided as to have a forward direction from said first internal node toward said second internal node,

a second poly-diode element having said forward direction and serially connected to said first poly-diode element, and

a capacitor having a first electrode being connected to a connection node between said first and second poly-diode elements and a second electrode being supplied with said clock signal,

a first output node to be supplied with a first output potential being lower than said second power supply potential by said pumping portion;

a second output node to be supplied with a second output potential being higher than said first power supply potential by said pumping portion; and

a operation mode switching circuit controlling a supply of potentials to said first internal node, said second internal node, said first output node and said second output node,

said operation mode switching circuit supplying said second power supply potential to said second internal node and outputting said first output potential from said first internal node to said first output node in a first operation mode while supplying said first power supply potential to said first internal node and outputting said second output potential from said second internal node to said second output node in a second operation mode.

2. The charge pump circuit in accordance with claim 1, further comprising an insulator film provided on a major surface of said semiconductor substrate;

wherein said poly-diode elements have P-type and N-type layers provided on said insulator film,

said charge pump circuit further comprising;

an interlayer isolation film provided on said major surface of said semiconductor substrate to cover said poly-diode elements and formed with first and second contact holes exposing said P-type and N-type layers respectively;

a first resistive element provided in said first contact hole and connected to said P-type layer;

a second resistive element provided in said second contact hole and connected to said N-type layer;

a first interconnection layer connected to said P-type layer through said first resistive element; and

a second interconnection layer connected to said N-type layer through said second resistive element.

3. The charge pump circuit in accordance with claim 1, wherein

said operation mode switching circuit includes:

a first switching circuit connected between said first power supply node and said first internal node,

a second switching circuit connected between said first internal node and said first output node,

a third switching circuit connected between said second power supply node and said second internal node, and

a fourth switching circuit connected between said second internal node and said second output node,

for bringing said second and third switching circuits into conducting states and bringing said first and fourth switching circuits into open states in said first operation mode while bringing said first and fourth switching circuits into conducting states and bringing said second and third switching circuits into open states in said second operation mode.

4. The charge pump circuit in accordance with claim 3, wherein

said first switching circuit includes:

a MOS transistor connecting said first internal node with said first power supply node in said second operation mode, and

said second switching circuit includes;

a MOS transistor connecting said first internal node with said first output node in said first operation mode.

5. The charge pump circuit in accordance with claim 3, wherein

said second switching circuit includes:

a first level conversion circuit converting a low potential level of a logic amplitude of a first control signal to the potential of said first internal node and outputting the same,

a second level conversion circuit converting said low potential level of said logic amplitude of said first control signal to the potential of said first output node and outputting the same, and

first and second N-channel MOS transistors, being serially connected between said first internal node and said first output node, receiving outputs of said first and second level conversion circuit in gates thereof respectively,

a back gate of said first N-channel MOS transistor is connected to said first internal node, and

a back gate of said second N-channel MOS transistor is electrically connected to said first output node.

6. The charge pump circuit in accordance with claim 3, wherein

said second switching circuit includes:

a diode electrically connecting said first output node and said first internal node with each other when the potential of said first output node is higher than that of said first internal node, and

a capacitor having a first electrode being connected to said first internal node and a second electrode being supplied with said clock signal when an output potential is produced at said first output node.

7. The charge pump circuit in accordance with claim 3, wherein

said third switching circuit includes:

a MOS transistor connecting said second internal node with said second power supply node in said first operation mode, and

said fourth switching circuit includes;

a MOS transistor connecting said second internal node with said second output node in said second operation mode.

8. The charge pump circuit in accordance with claim 3, wherein

said fourth switching circuit includes:

first level conversion circuit converting a high potential level of a logic amplitude of a first control signal to the potential of said second internal node and outputting the same,

second level conversion circuit converting said high potential level of said logic amplitude of said first control signal to the potential of said second output node and outputting the same, and

first and second P-channel MOS transistors, being serially connected between said second internal node and said second output node, receiving outputs of said first and second level conversion circuits in gates thereof respectively,

a back gate of said first P-channel MOS transistor is connected to said second internal node, and

a back gate of said second P-channel MOS transistor is electrically connected to said second output node.

9. The charge pump circuit in accordance with claim 3, wherein

said fourth switching circuit includes:

a diode electrically connecting said second output node and said second internal node with each other when the potential of said second output node is lower than that of said second internal node, and

a capacitor having a first electrode being connected to said second internal node and a second electrode being supplied with said clock signal when an output potential is produced at said second output node.

10. The charge pump circuit in accordance with claim 3, wherein

said capacitor has:

a first conductivity type well region provided on said semiconductor substrate,

an oxide film provided on a major surface of said semiconductor substrate to partially cover said well region,

an electrode provided to cover said oxide film, and

a second conductivity type impurity region provided on said well region and in contact with a lower region of said electrode,

said well region and said second conductivity type impurity region being electrically connected with each other.

11. A nonvolatile semiconductor memory device provided on a semiconductor substrate, comprising:

a nonvolatile semiconductor element, having a control gate and a floating gate; and

a charge pump circuit supplying prescribed potentials to said nonvolatile semiconductor element for storage and erase operations,

said charge pump circuit including

a first power supply node receiving a first power supply potential,

a second power supply node receiving a second power supply potential being lower than said first power supply potential,

a pumping portion having a first and a second internal nodes, driven by a dock signal and rendering the potential of said second internal node higher than that of a first internal node,

said pumping portion having

a first poly-diode element so provided as to have a forward direction from said first internal node toward said second internal node,

a second poly-diode element having said forward direction and serially connected to said first poly-diode element, and

a first capacitor having a first electrode being connected to a connection node between said first and second poly-diode elements and a second electrode being supplied with said clock signal,

a first output node to be supplied with a first output potential being lower than said second power supply potential by said pumping portion,

a second output node to be supplied with a second output potential being higher than said first power supply potential by said pumping portion, and

a operation mode switching circuit controlling a supply of potentials to said first internal node, said second internal node, said first output node and said second output node,

said operation mode switching circuit supplying said second power supply potential to said second internal node and outputting said first output potential from said first internal node to said first output node in a first operation mode while supplying said first power supply potential to said first internal node and outputting said second output potential from said second internal node to said second output node in a second operation mode.

12. The nonvolatile semiconductor memory device in accordance with claim 11, further comprising an insulator film provided on a major surface of said semiconductor substrate, wherein

said poly-diode elements have P-type and N-type layers provided on said insulator film,

said nonvolatile semiconductor memory device further comprising:

an interlayer isolation film provided on said major surface of said semiconductor substrate to cover said poly-diode elements and formed with first and second contact holes exposing said P-type and N-type layers respectively,

a first resistive element provided in said first contact hole and connected to said P-type layer,

a second resistive element provided in said second contact hole and connected to said N-type layer,

a first interconnection layer connected to said P-type layer through said first resistive element, and

a second interconnection layer connected to said N-type layer through said second resistive element.

13. The nonvolatile semiconductor memory device in accordance with claim 11, wherein

said operation mode switching circuit includes:

a first switching circuit connected between said first power supply node and said first internal node,

a second switching circuit connected between said first internal node and said first output node,

a third switching circuit connected between said second power supply node and said second internal node, and

a fourth switching circuit connected between said second internal node and said second output node,

for bringing said second and third switching circuits into conducting states and bringing said first and fourth switching circuits into open states in said first operation mode while bringing said first and fourth switching circuits into conducting states and bringing said second and third switching circuits into open states in said second operation mode.

14. The nonvolatile semiconductor memory device in accordance with claim 13, wherein

said poly-diode elements are formed integrally with said first electrode of said first capacitor in the same step as that for said floating gate.

15. The nonvolatile semiconductor memory device in accordance with claim 13, wherein

said first capacitor further has:

a first conductivity type well region provided on said semiconductor substrate,

an oxide film held between a major surface of said well region and said first electrode, and

a second conductivity type impurity region provided in said well region and in contact with lower regions of said electrodes,

said well region, said second conductivity type impurity region and said second electrode being electrically connected with each other.

16. The nonvolatile semiconductor memory device in accordance with claim 13, wherein

said pumping portion further includes:

fourth, fifth and sixth internal nodes provided on a path for feeding said current from said first internal node toward said second internal node,

a third poly-diode element provided to feed a current from said fourth internal node toward said fifth internal node,

a second capacitor connected between a first clock node supplied with a signal being complementary to said clock signal and said fourth internal node,

a fourth poly-diode element provided to feed said current from said fifth internal node toward said sixth internal node,

a third capacitor connected between a second clock node supplied with said clock signal and said fifth internal node,

a fifth poly-diode element provided to feed said current from said sixth internal node toward said second internal node, and

a fourth capacitor connected between said first clock node and said sixth internal node,

said first poly-diode element is connected between said first and third internal nodes,

said second poly-diode element is connected between said third and fourth internal nodes,

said first capacitor is connected between said second clock node and said third internal node,

said first and third capacitors are formed in a first well region being electrically connected with said second clock node, and

said second and fourth capacitors are formed in a second well region being electrically connected with said first clock node.

17. The nonvolatile semiconductor memory device in accordance with claim 13, wherein

said pumping portion further includes:

fourth, fifth and sixth internal nodes provided on a path for feeding said current from said first internal node toward said second internal node,

a third poly-diode element provided to feed a current from said fourth internal node toward said fifth internal node,

a second capacitor connected between a first clock node supplied with a signal being complementary to said clock signal and said fourth internal node,

a fourth poly-diode element provided to feed said current from said fifth internal node toward said sixth internal node,

a third capacitor connected between a second clock node supplied with said clock signal and said fifth internal node,

a fifth poly-diode element provided to feed said current from said sixth internal node toward said second internal node, and

a fourth capacitor connected between said first clock node and said sixth internal node,

said first poly-diode element is connected between said first and third internal nodes,

said second poly-diode element is connected between said third and fourth internal nodes,

said first capacitor is connected between said second clock node and said third internal node,

electrodes of said first and third capacitors connected to said second clock node are integrally formed in the same step as that for said control gate of said nonvolatile semiconductor element, and

electrodes of said second and fourth capacitors connected to said first clock node are integrally formed in the same step as that for said control gate of said nonvolatile semiconductor element.