Apparatus for synchronizing master and slave processors

• US 6,147,562 A
• Filed: 05/26/1999
• Issued: 11/14/2000
• Est. Priority Date: 11/26/1996
• Status: Expired due to Fees

• Current Assignee: Nokia Siemens Networks GmbH & Company KG (Nokia Corporation)
• Original Assignee: Siemens AG
• Inventors: Quirmbach, Gerhard
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US09/308,947
• Time in Patent Office: 538 Days
• Field of Search: 331/10-12, 331/14, 331/17, 331/18, 331/25, 327/147-150, 327/298
• US Class Current: 331/14
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A master and slave arrangement of processors includes a clock signal synchronization apparatus. The clock signals of two (processor) assemblies in micro-synchronous operation are only allowed to exhibit an extremely slight phase difference. A system clock signal is generated by a voltage controlled oscillator, which is fed by phase detectors with a filter at the output of each phase detector. Switches are provided between the filter output and the voltage controlled oscillator input. The phase detectors compare the system clock signal and a reference clock signal. A delay is provided at the input of one phase detector.

Claims

1. A synchronization apparatus of an assembly that generates a system clock signal which is synchronized to one of a plurality of reference clocks, comprising:

a voltage controlled oscillator having a control input and that generates the system clock signal of the assembly dependent on a signal at said control input;

an arrangement including phase detectors each having two inputs and an output, a respective reference clock signal applied to one of said two inputs of each of said phase detectors and the system clock signal being applied to the other of said two inputs;

filters having inputs connected to said outputs of said phase detectors and having outputs;

switches connected at said outputs of said filters to connect signals output from said filters to said control input of said voltage controlled oscillator;

an operating controller connected to said switches that controls said switches such that respectively one of the output signals of the filters is through-connected to the control input of the VCO, and

further switches connected to said operating controller which controls said further switches such that, given a case wherein the output signal of a respective one of the filters is not through-connected to the input of the VCO,

the output of a respective on of the phase detectors is switched to tri-state;

the output signal is fed back to a first input of said respective one of said filters;

and a decoupled signal of the control input of the VCO is applied to a second input of said respective one of said filters.

2. A synchronization unit according to claim 1, further comprising:

a delay unit that delays the system clock before input to a phase detector of the phase detectors by a running time difference between the reference clock of the phase detector of the phase detectors and the system clock.

3. A method for synchronizing clock signals in a master/slave arrangement, comprising the steps of:

generating a system clock signal depending on an input control signal;

providing reference clock signals;

detecting a phase difference between each of the reference clock signals and the system clock signal to obtain phase difference signals;

filtering said phase difference signals with a filter to obtain filter signals;

selectively connecting one of said filter signals as said input control signal;

providing a tri-state output of said phase difference detecting step;

feeding said filter signals of said filtering step back to a further filter to synchronize said system clock to one of a plurality of reference clocks.