Multi-chip module having printed wiring board comprising circuit pattern for IC chip

• US 6,147,876 A
• Filed: 06/13/1996
• Issued: 11/14/2000
• Est. Priority Date: 09/14/1993
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamaguchi, Masayoshi, Hohki, Kazutoshi, Sawano, Mitsutoshi
• Primary Examiner(s): Sough, Hyung Sub
• Assistant Examiner(s): Vigushin, John B.
• Application Number:
  US08/617,843
• Time in Patent Office: 1,615 Days
• Field of Search: 174/35 R, 174/35 GC, 174/260, 174/261, 174/262, 174/263, 174/265, 174/266, 257/698, 257/700, 257/701, 257/723, 257/724, 257/728, 257/730, 257/772, 257/774, 257/778, 257/786, 257/759, 257/779, 228/180.21, 361/784, 361/790, 361/791, 361/803, 361/805, 361/818, 361/748-751, 361/761-764, 361/766, 361/780, 361/782, 361/792-795, 361/768, 439/44, 439/45, 439/65, 439/68, 439/69, 439/71, 439/74, 439/541.5, 333/185, 333/246, 333/247
• US Class Current: 361/766
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/147 : at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit H05K1/148 takes precedence
• CPC Class Codes: H05K 2201/09181 : Notches in edge pads
• CPC Class Codes: H05K 2201/09536 : Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 3/3442 : having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: H05K 3/368 : parallel to each other H05K3/361 takes precedence
• CPC Class Codes: H05K 3/4614 : the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: H05K 3/4623 : the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence

Abstract

Bare IC chips (201 through 203) are mounted on respective areas (101 through 103) of a printed wiring board (100). The outer electrode pads (105) on the peripheries of the board (100) are soldered to another printed wiring board (1) such as a mother board. Lead pads (107) and the outer electrode pads (105) are interconnected through a circuit pattern (109), through holes (111) and interstitial via holes (112). The circuit pattern (109) is disposed on a die bonding surface of the bare IC chips (201 and 202) for which insulation is not necessary. A multi-chip module is thus completed.

Claims

1. A multi-chip module which comprises a printed wiring board and a plurality of bare IC chips mounted on a predetermined area of the printed wiring board, the multi-chip module being mounted on a main printed wiring board, wherein:

the printed wiring board has a multilayer structure including a plurality of inner layers; and

the multi-chip module further comprises;

a first resistor element both ends of which are electrically connected to a conductive pattern provided on one of the inner layers; and

a second printed resistor element printed on an area other than the predetermined area of the printed wiring board for adjusting a characteristic of the resistors provided in the multi-chip module including the first resistor element.

2. A multi-chip module which comprises a printed wiring board and a plurality of bare IC chips mounted on a predetermined area of the printed wiring board, the multi-chip module being mounted on a main printed wiring board, wherein:

the printed wiring board has a multilayer structure including a plurality of inner layers; and

the multi-chip module further comprises;

a first dielectric element both sides of which are electrically connected to a conductive pattern provided on one of the inner layers so that a formed capacitor is formed by the dielectric element and the conductive pattern; and

a second dielectric element printed on an area other than the predetermined area of the printed wiring board for adjusting a characteristic of the capacitors provided in the multi-chip module including the formed capacitor.

3. A multi-chip module which comprises a printed wiring board and a plurality of bare IC chips mounted on a predetermined area of the printed wiring board, the multi-chip module being mounted on a main printed wiring board, wherein:

the printed wiring board has a multilayer structure including a plurality of inner layers; and

the multi-chip module further comprises;

a first resistor element both ends of which are electrically connected to a conductive pattern provided on one of the inner layers;

a first dielectric element both sides of which are electrically connected to a conductive pattern provided on one of the inner layers so that a formed capacitor is formed by the dielectric element and the conductive pattern;

a second printed resistor element printed on an area other than the predetermined area of the printed wiring board for adjusting a characteristic of the resistors provided in the multi-chip module including the first resistor element, and

a second dielectric element printed on an area other than the predetermined area of the printed wiring board for adjusting a characteristic of the capacitors provided in the multi-chip module including the formed capacitor.