Output feedback and under-voltage detection

• US 6,147,883 A
• Filed: 11/16/1998
• Issued: 11/14/2000
• Est. Priority Date: 11/16/1998
• Status: Expired due to Term

• Current Assignee: Powers Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Lund, Leif, Balakrishnan, Balu, Djenguerian, Alex
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/192,960
• Time in Patent Office: 729 Days
• Field of Search: 363/49, 363/50, 363/55, 363/56, 323/313, 323/315, 323/276, 323/282
• US Class Current: 363/49
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence

Abstract

A switched mode controller for properly handling an under-voltage condition in a power line which includes a current mirror for receiving current from the power line; a reference current source coupled to the current mirror for supplying a reference current; and a power transistor coupled to the reference current source, the power transistor generating a pulse width modulated signal when current from the power line exceeds the reference current, the power transistor being disabled when current from the power line is less than the reference current.

Claims

1. A circuit for detecting an under-voltage condition at a voltage input of a power supply, comprising:

a current mirror coupled to receive a current representing the voltage input of the power supply; and

a reference current source to generate a reference current coupled to be received by the current mirror to generate an under-voltage signal when the reference current exceeds the current representing the voltage input of the power supply, the power supply being disabled when the under-voltage signal is generated.

2. The circuit of claim 1 wherein the under-voltage condition is detected during power up and/or during an off cycle of an auto-restart operation of the power supply.

3. The circuit of claim 1 further comprising a resistor coupled between the power supply voltage input and the current mirror.

4. The circuit of claim 1 further comprising a resistor coupled between the power supply voltage input and an electrical terminal.

5. The circuit of claim 4 wherein the current mirror further comprises:

a first transistor having a gate and a drain, the gate being coupled to the drain; and

a second transistor having a gate, the gate of the second transistor coupled to the gate of the first transistor.

6. The circuit of claim 5 further comprising a first isolation transistor coupled between the electrical terminal and the first transistor drain.

7. The circuit of claim 6 further comprising:

a second current source; and

a second isolation transistor coupled between the second current source and the electrical terminal to receive a feedback signal.

8. The circuit of claim 7 further comprising a latch coupled to the output of the second reference current source to receive the feedback signal.

9. The circuit of claim 7 wherein the electrical terminal receives both the feedback signal and the under-voltage signal.

10. The circuit of claim 9 wherein only one of the first and second isolation transistors conducts at a time.

11. A regulator circuit connected in series with a transformer primary winding to an input voltage, the regulator circuit comprising:

a resistor coupled to the input voltage, the resistor providing an input current representing the input voltage;

a current mirror coupled to the resistor for mirroring the input current; and

a reference current source to generate a reference current coupled to be received by the current mirror to generate an under-voltage signal when the reference current exceeds the input current, the power supply being disabled when the under-voltage signal is generated.

12. The regulator circuit of claim 11 wherein the under-voltage signal is detected during power up and/or during an off cycle in an auto-restart operation of the regulator circuit.

13. The regulator circuit of claim 11 further comprising a first isolation transistor coupled between the resistor and the current mirror.

14. The regulator circuit of claim 11 wherein the current mirror further comprises:

a first transistor having a gate and a drain, the gate being coupled to the drain; and

a second transistor having a gate, the gate of the second transistor coupled to the gate of the first transistor.

15. The regulator circuit of claim 13 further comprising a second reference current source.

16. The regulator circuit of claim 15 further comprising a second isolation transistor coupled between the second current source and the resistor.

17. The regulator circuit of claim 15 further comprising a latch coupled to the output of the second reference current source for receiving a feedback signal.

18. The regulator circuit of claim 16 wherein each of the first and second isolation transistors conducts one at a time.

19. The regulator circuit of claim 11, wherein the feedback signal and the under-voltage signal is received by one electrical terminal.

20. The regulator circuit of claim 11 further comprising a power switching transistor coupled to the under-voltage signal.