Method and apparatus for low-power charge transition in an I/O system of an integrated circuit

• US 6,147,884 A
• Filed: 01/27/2000
• Issued: 11/14/2000
• Est. Priority Date: 06/28/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Walia, Rajan
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/492,511
• Time in Patent Office: 292 Days
• Field of Search: 363/59, 363/60, 307/109, 307/110, 327/108, 327/111, 327/284
• US Class Current: 363/59
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

Method and apparatus for low-power charge transition in an I/O system of an integrated circuit comprising an interconnected linking of stepwise charging and charge recycling of capacitive loads. The I/O system according to the invention does not need additional pins for recycling capacitors, additional silicon area for on-chip capacitors, or additional power supplies. This I/O system achieves power savings of 20% to 30% of CV² f.

Claims

1. Method for low-power charge transition in an integrated-circuit I/O system which comprises a plurality of capacitive loads which convert between a charged state at an operating voltage and a discharged state at ground during each of operation cycles of the I/O system, wherein the operation cycles are predetermined by an external clock signal, and of which plurality of said capacitive loads a first number of capacitive loads having the charged state converts from the charged state to the discharged state at ground, and a second number of capacitive loads having the discharged state converts from the discharged state to the charged state at the operating voltage, the method comprising the steps of:

sharing the charge of said first number of capacitive loads having the charged state between said first number of capacitive loads and said second number of capacitive loads having the discharged state, thereby charging said second number of capacitive loads from ground to a preload voltage and discharging said first number of capacitive loads from said operating voltage to said preload voltage,

charging said second number of capacitive loads having been charged to said preload voltage from said preload voltage to an intermediate voltage between said preload voltage and said operating voltage, and

charging said second number of capacitive loads having been charged to said intermediate voltage from said intermediate voltage to said operating voltage.

2. Method according to claim 1, further comprising the step of discharging said first number of capacitive loads from said operating voltage to ground.

3. Method according to claim 1, wherein the step of sharing the charge comprises the steps of:

connecting said first number of capacitive loads to said second number of capacitive loads for a predetermined first duration by respective transmission gates and control units assigned thereto, thereby sharing the charge stored in said first number of capacitive loads between said first number of capacitive loads and said second number of capacitive loads, wherein said control units provide said transmission gates with a transmission signal turning on said transmission gates for bidirectional current flow for said predetermined first duration.

4. Method according to claim 3, wherein said first number of capacitive loads and said second number of capacitive loads are connected via said transmission gates to a common charge sharing bus.

5. Low-power I/O system of an integrated circuit for low-power charge transition in said I/O system, comprising

a plurality of capacitive loads which convert between a charged state at an operating voltage and a discharged state at ground during each of the operation cycles of said I/O system, wherein the operation cycles are predetermined by an external clock signal, and of which plurality of said capacitive loads a first number of capacitive loads having said charged state converts from said charged state to said discharged state at ground and a second number of capacitive loads having said discharged state converts from said discharged state to said charged state at the operating voltage,

an intermediate power supply for providing an intermediate voltage,

an operating power supply for providing an operating voltage,

and per each capacitive load

a transmission gate connected to said capacitive load for connecting said first number of capacitive loads to said second number of capacitive loads,

an intermediate driver connected between said capacitive load and said intermediate power supply,

an operating driver connected between said capacitive load and said operating power supply, and

a control unit connected to said transmission gate, said intermediate driver and said operating driver,

wherein the control units sequentially connect said second number of capacitive loads to said first number of capacitive loads through said transmission gates for a first duration by controlling the respective transmission gates, to said intermediate power supply for a second duration by controlling the respective intermediate drivers, and to said operating power supply for a third duration by controlling the respective operating drivers.

6. Low-power I/O system according to claim 5, further comprising a charge sharing bus, wherein said transmission gates are connected to said charge sharing bus through which charge sharing is performed between said first number of capacitive loads and said second number of capacitive loads when the said transmission gates are turned on by the respective control units.

7. I/O system according to claim 5, wherein said control units are formed as a single control device and arranged together with said transmission gates, said intermediate drivers and said operating drivers on one integrated circuit chip.

8. I/O system according to claim 7, wherein said integrated circuit chip further comprises said capacitive loads.

9. I/O system according to claim 7, wherein said integrated circuit chip further comprises said intermediate power supply and said operating power supply.