Nonvolatile semiconductor memory device

• US 6,147,911 A
• Filed: 02/04/2000
• Issued: 11/14/2000
• Est. Priority Date: 11/13/1995
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takeuchi, Ken, Tanaka, Tomoharu
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/497,889
• Time in Patent Office: 284 Days
• Field of Search: 365/185.28, 365/185.23, 365/185.04, 365/185.11, 365/185.17, 365/185.18
• US Class Current: 365/185.28
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

A non-volatile semiconductor memory device comprising a memory cell array having a plurality of electrically writable memory cells arranged in a matrix form, each of the memory cells having three or more logic states so as to store a multi-value data "i" (i=0, 1, . . . , n-1: n≧3), a plurality of data latch circuits for temporarily storing data controlling a write state of the plurality of memory cells of the memory array, write verify circuit for confirming the write state of the plurality of memory cells, and an "i" data batch verify circuit for batch-detecting whether or not the memory cell where data "i" should be written reaches a memory state of data "i."

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell section including at least one memory cell;

a first signal line transferring data from/to said memory cell section; and

a first select transistor arranged between said first signal line and said memory cell section, wherein

in case of a program inhibit operation, a write unselect voltage is applied to said first signal line and the write unselect voltage is transferred to a channel of at least said memory cell section by applying a first select gate voltage higher than the write unselect voltage to a gate of said first select transistor, and then a voltage higher than the first select gate voltage is applied to a control gate of said memory cell to generate a write inhibit channel voltage boosted by a capacitive coupling of the channel of said memory cell with the control gate thereof.

2. The device according to claim 1, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell/said first select transistor.

3. The device according to claim 1, wherein the write unselect voltage is a power supply voltage.

4. The device according to claim 3, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell/said first select transistor.

5. A non-volatile semiconductor memory device comprising:

a memory cell section including at least one memory cell;

a first signal line transferring data from/to said memory cell section; and

a first select transistor arranged between said first signal line and said memory cell section, wherein

in case of a program inhibit operation, a write unselect voltage is applied to said first signal line and the write unselect voltage is transferred to a channel of said memory cell section by applying a first select gate voltage higher than the write unselect voltage to a gate of said first select transistor and a control gate of said memory cell, and then a voltage higher than the first select gate voltage is applied to the control gate of said memory cell to generate a write inhibit channel voltage boosted by a capacitive coupling of the channel of said memory cell with the control gate thereof.

6. The device according to claim 5, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell/said first select transistor.

7. The device according to claim 5, wherein the write unselect voltage is a power supply voltage.

8. The device according to claim 7, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell/said first select transistor.

9. A non-volatile semiconductor memory device comprising:

a memory cell section including a plurality of memory cells which are connected in series;

a first common signal line transferring data from/to said memory cell section; and

a first select transistor arranged between said first common signal line and said memory cell section, wherein

in case of a program inhibit operation, a wire unselect voltage is applied to said first common signal line and the write unselect voltage is transferred to a channel of said memory cell section by applying a first select gate voltage higher than the write unselect voltage to a gate of said first select transistor and control gates of said plurality of memory cells, and then a pass voltage higher than the first select gate voltage is applied to the control gates of the unselected memory cells and a program voltage higher than the pass voltage is applied to the control gate of the selected memory cell to generate a write inhibit channel voltage boosted by a capacitive coupling of the channel of said plurality of memory cells with the control gates thereof.

10. The device according to claim 9, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell/said first select transistor.

11. The device according to claim 9, wherein the write unselect voltage is a power supply voltage.

12. The device according to claim 11, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell/said first select transistor.

13. A non-volatile semiconductor memory device comprising:

a memory cell section including a least one memory cell;

a first signal line transferring data from/to said memory cell section; and

a first select transistor arranged between said first signal line and said memory cell section, wherein

in case of a program inhibit operation, a write unselect voltage is applied to said first signal line and the write unselect voltage is transferred to a channel of said memory cell section by applying a first select gate voltage higher than the write unselect voltage to a gate of said first select transistor and applying a first control gate voltage which differs from the first select gate voltage to a control gate of said memory cell, and then a voltage higher than the first select gate voltage is applied to the control gate of said memory cell to generate a write inhibit channel voltage boosted by a capacitive coupling of the channel of said memory cell with the control gate thereof.

14. The device according to claim 13, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said first select transistor and the first control gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell.

15. The device according to claim 14, wherein the write unselect voltage is a power supply voltage.

16. The device according to claim 15, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said first select transistor and the first control gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell.

17. A non-volatile semiconductor memory device comprising:

a memory cell section including a plurality of memory cells which are connected in series;

a first common signal line transferring data from/to said memory cell section; and

a first select transistor arranged between said first common signal line and said memory cell section, wherein

during a program operation, in the case that said memory cell section is write-selected, a write select voltage is applied to said first common signal line, and in the case that said memory cell section is write-inhibited, a write unselect voltage is applied to said first common signal line, and the write unselect voltage is transferred to a channel of said write-inhibited memory cell section by applying a first select gate voltage higher than the write unselect voltage to a gate of said first select transistor and control gates of said plurality of memory cells, and then a pass voltage higher than the first select gate voltage is applied to the control gates of the unselected memory cells and a program voltage higher than the pass voltage is applied to the control gate of the selected memory cell so that said write-selected memory cell section is boosted by a capacitive coupling of the channel of said plurality of memory cells with the control gates thereof.

18. The device according to claim 17, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell/said first select transistor.

19. The device according to claim 17, wherein the write unselect voltage is a power supply voltage.

20. The device according to claim 19, wherein the first select gate voltage is higher than the write unselect voltage by a threshold voltage of said memory cell/said first select transistor.

21. The device according to claim 17, wherein the write select voltage is lower than the write unselect voltage.

22. The device according to claim 17, wherein the write select voltage is 0V and the write unselect voltage is a power supply voltage.