Communications system for driving pairs of twisted pair links

• US 6,147,963 A
• Filed: 07/11/1997
• Issued: 11/14/2000
• Est. Priority Date: 07/11/1996
• Status: Expired due to Term

• Current Assignee: 4Links Limited
• Original Assignee: 4 Links For Technical Help
• Inventors: Walker, Christopher Paul Hulme, Cook, Barry Michael
• Primary Examiner(s): Patel, Ajit
• Assistant Examiner(s): NGUYEN, BRIAN D
• Application Number:
  US08/893,860
• Time in Patent Office: 1,222 Days
• Field of Search: 370/200, 370/419, 370/439, 370/357, 370/366, 370/367, 370/368, 370/513, 370/514, 375/293, 375/257, 375/258
• US Class Current: 370/200
• CPC Class Codes: H03M 5/16 the pulses having three levels
• CPC Class Codes: H04B 3/02 Details
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes
• CPC Class Codes: H04L 5/20 using different combinations of lines, e.g. phantom working

Abstract

A communication system includes two high speed communication links formed by pairs of transformers at either end thereof. A phantom circuit formed by the pairs of transformers is used to distribute power to devices connected to the high speed links. In transmission part of a communications system, data is transmitted under the control of a continuously variable frequency clock. Transmission is on parallel data-strobe links, and the receive includes circuitry to identify on which parallel the data signal is preset. A method and circuitry is provided for transmitting and receiving dc balanced data strobe signals.

Claims

1. A communications system comprising:

a first high speed link having a first transformer interface at a transmit end and a second transformer interface at a receive end;

a second high speed link having a third transformer interface at a transmit end and a fourth transformer interface at a receive end;

a low speed link comprising a phantom circuit formed by the first to fourth transformers, the transmit end of the low speed link being formed by connections to the centre taps of the first and third transformers and the receive end of the low speed link being formed by connections to the centre taps of the second and fourth transformers;

wherein the transmit end of the low speed link is connected to a power supply and wherein the transmit end of the low speed link comprises a switch for periodically interrupting the power supplied from said power supply, at least one of the high speed links being connected to a device at the receive end for receiving signals from the respective high speed link, the receive end of the low speed link being capable of providing power and signals to the device from the power supply.

2. A communications interface comprising:

output circuitry for providing two parallel outputs, one in the form of a data signal and one in the form of a strobe signal and including strobe generation circuitry, wherein the data signal comprises a serial bit pattern and the strobe generation circuitry generates the strobe signal such that the strobe signal has signal transitions only at bit boundaries where there is no transition on the data signal, the strobe generation circuitry being controlled by a clock signal such that for each clock pulse where there is no signal transition in the data signal a signal transition is generated in the strobe signal, the frequency of the clock signal being continuously variable; and

input circuitry having two inputs for receiving data and strobe signals, and including an exclusive-or circuit for receiving the data and strobe signals and generating a receive clock on the output thereof, the receive clock being generated with clock signal transitions having a timing matching that at which the strobe and data signals were transmitted.

3. Data receiving circuitry comprising:

input circuitry having two inputs, one input for receiving a data signal and the other input for receiving a strobe signal, the strobe signal being parallel to the data signal and having signal transitions only at bit boundaries where there is no transition on the data signal;

an exclusive-or gate, having inputs connected to the two inputs, and generating a receive clock on the output thereof;

detection circuitry having two inputs coupled to the respective two inputs of the input circuitry and for detecting an expected bit sequence associated with the data signal on one of said two inputs;

output circuitry for outputting the data signal under the control of the receive clock; and

selection circuitry for connecting the one of said inputs on which said sequence is detected to the output circuit.

4. A method of establishing parallel data and strobe signal communication paths having dc balanced data and strobe signals on each path, comprising:

generating a binary data signal comprising signal level transitions at predetermined bit boundaries;

generating and supplying a binary strobe signal, parallel to the binary data signal, having signal transitions at bit boundaries other than said predetermined bit boundaries on the parallel binary data signal; and

encoding the binary data signal into a ternary data signal and the binary strobe signal into a ternary strobe signal, each said ternary signal comprising a sequence of trits and being dc balanced for transmission, wherein the step of encoding the binary data signal and the binary strobe signal into respective ternary dc balanced signals encodes such signals such that only single level logic transitions are permitted between successive trits of the ternary signals.

5. The method of claim 4, wherein the encoding step comprises the steps of, for each of the data and strobe signal:

calculating the running digital sum of the ternary signal;

transmitting next binary 1 as ternary -1 if the running digital sum is positive and at least two 0'"'"'s have been transmitted since the last ternary +1;

transmitting the next binary 1 as ternary +1 if the running digital sum is negative and at least two 0'"'"'s have been transmitted since the last ternary -1;

transmitting at least two successive binary 1'"'"'s as ternary -1'"'"'s if the running digital sum is positive and the at least two binary 1'"'"'s follow any number of 0'"'"'s;

transmitting at least two successive binary 1'"'"'s as ternary +1'"'"'s if the running digital sum is negative and the at least two binary 1'"'"'s follow any number of 0'"'"'s; and

otherwise reversing the polarity of each ternary 1 each time a run of at least one 0 occurs.

6. The method of claim 4, wherein when there is no data to transmit, the encoding step comprises generating extra ternary signals on each of the data and strobe signal communication paths until the running digital sum on each of said paths becomes zero, and then ceasing to generate further ternary signals on said paths.

7. The method of claim 4, wherein the step of outputting the binary data signal comprises:

receiving n binary bits to be transmitted;

adding a flag bit to the n binary bits to form a n+1 bit binary code-word;

calculating the running digital sum of successively formed binary code-words;

outputting as the binary data signal successive code-words in which the n binary bits are in an inverted or non-inverted state depending on the current running digital sum of the binary code-words, the flag bit being set to indicate inverted data.

8. The method of claim 7, wherein those code-words having non-zero disparity are inverted or not so as to reduce the magnitude of the running digital sum at code-word boundaries.

9. The method of claim 7, wherein n=8.

10. The method of claim 7, wherein said adding step includes adding a parity bit to form a n+2 bit code-word.

11. The method of claim 10, wherein the value of the parity bit is selected to ensure an odd number of 1'"'"'s in the code-word.

12. The method of claim 10, wherein those binary code-words having zero disparity are not inverted.

13. The method of claim 10, wherein for those code-words having zero disparity, the code-words containing the inverse data with the flag bit set are reserved for control purposes.

14. The method of claim 10, wherein for those code-words having zero disparity, the code-words containing the inverse data thereof with the flag bit set are used to substitute code-words to limit the running digital sum at boundaries of the binary code-words.

15. The method of claim 10, wherein for those code-words having zero disparity, the code-words containing the inverse data thereof with the flag bit set are used to substitute code-words to minimise the run length on the ternary data and strobe signals.

16. Data transmission circuitry comprising:

input circuitry for receiving a binary data signal, said binary data signal comprising signal level transitions at predetermined bit boundaries;

strobe generation circuitry for generating a binary strobe signal, parallel to the binary data signal, and having signal transitions at bit boundaries other than said predetermined bit boundaries on the parallel binary data signal;

encoding circuitry for encoding the binary data signal into a ternary data signal and the binary strobe signal into a ternary strobe signal, wherein said ternary signals each comprise a sequence of trits and are dc balanced; and

output circuitry for transmitting the ternary encoded data and strobe signals, wherein the input circuitry receives n binary bits to be transmitted and further comprises;

bit generation circuitry for generating a flag bit associated with the n binary bits;

addition circuitry for adding the flag bit to the n binary bits to form a binary code-word;

calculation circuitry for calculating the running digital sum of successively formed binary code-words;

inversion circuitry for inverting the n binary bits of data in a code-word in dependance on the current running digital sum and for setting the flag bit to indicate inverted data; and

outputting as the binary data signal successive code-words.

17. Data transmission circuitry according to claim 16, further comprising calculation circuitry to calculating the disparity of a code-word, wherein the disparity of a code-word is zero the data therein is not inverted.

18. Data transmission circuitry according to claim 16, wherein the bit generation circuitry further generates a parity bit and the addition circuitry further adds the parity bit to the n binary bits and the flag bit to form a n+2 bit binary code-word.

19. Data transmission circuitry according to claim 16, further comprising control circuitry for controlling the inversion circuitry to invert the data in a code-word in dependence on the running digital sum at code-word boundaries.

20. Data transmission circuitry according to claim 16, further comprising substitution storage means for storing those code-words having zero disparity and their flag bits set to indicate inversion of the data therein, such code-words being used to substitute for code-words which increase the running digital sum at code-word boundaries or the run length of the data signal.

21. A method of decoding a ternary data signal and a parallel ternary strobe signal, said ternary data signal comprising a sequence of trits and carrying data comprising signal carrying timing information comprising signal level transitions at predetermined trit boundaries, said ternary strobe signal level transitions at trit boundaries other than said predetermined trit boundaries, the method comprising:

rectifying the ternary data signal into a binary data signal and the ternary strobe signal into a binary strobe signal;

exclusive-ORring the binary data and binary strobe signals to generate a receive clock signal; and

outputting the binary data signal under the control of the receive clock signal, wherein the ternary data signal comprises a plurality of code-words including a flag bit indicative of whether the data in the code-word is inverted or non-inverted, and further comprises the steps of;

inverting or not inverting the data in the received code-word in dependance on the flag bit of the code word.

22. The method of claim 21, wherein the received code-words further include a parity bit, the parity bit being set to ensure an odd number of ones in the code-word, the method further including the step of checking that the code-word includes an odd number of 1'"'"'s.

23. Data receiving circuitry comprising:

input circuitry for receiving a ternary data signal and a parallel ternary strobe signal, said ternary data signal comprising a sequence of trits and carrying data comprising signal level transitions at predetermined trit boundaries, said ternary strobe signal carrying timing information comprising signal level transitions at trit boundaries other than said predetermined trit boundaries;

rectification circuitry for rectifying the ternary data signal into a binary data signal and the ternary strobe signal into a binary strobe signal;

an exclusive-OR gate for receiving the binary data and binary strobe signals and generating a receive clock signal at its output; and

output circuitry for outputting the binary data signal under the control of the receive clock signal, wherein the received ternary data signal comprises code-words including ternary trits and a flag trit, the data receiving circuitry further comprising control means for receiving the flag trit and in dependance thereon inverting or not inverting the bits of data in the received code-word.

24. Data receiving circuitry according to claim 23, wherein the received ternary code-words include a parity trit the data receiving circuitry further comprising a parity check circuit, the parity check circuit checking the parity of the received code-word in dependence on the parity bit.

25. Data receiving circuitry according to claim 23, further comprising circuitry for calculating the disparity of each received code-word, wherein if the disparity of the code-word is zero and the flag bit of the code-word is set to indicate inversion, the data receiving circuitry further comprising storage means for storing code-words for substitution of code-words having zero disparity and their flag bits set.

26. Data receiving circuitry according to claim 23, further comprising inversion circuitry, wherein if the disparity of the code-word is non-zero and the flag bit is set, the inversion circuitry inverts the data contained in the code-word.