Receive path implementation for an intermediate frequency transceiver
First Claim
1. A wireless communication system, comprising:
- an antenna for receiving and transmitting radio-frequency (RF) signals;
frequency conversion circuitry for converting received RF signals into intermediate frequency (IF) signals and for converting output IF signals into transmitted RF signals;
an IF transceiver receiving IF signals from and outputting IF signals to said frequency conversion circuitry, said IF transceiver having a receive section including a complex delta-sigma analog-to-digital converter with a loop filter that has real and complex filters cascaded together; and
digital signal processing circuitry receiving and processing digital data from said IF transceiver.
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Accused Products
Abstract
A receive path implementation for an intermediate frequency (IF) transceiver is disclosed that provides increased signal processing integrity and accuracy with an efficient and improved design. A complex filter for a bandpass delta-sigma analog-to-digital converter (ADC) provides efficient complex noise shaping with a combination of real and complex filters. An automatic gain control (AGC) amplifier provides a constant bandwidth and zero variation phase shift for all gain levels. Clock adjust circuitry provides a clock signal with a jitter-free edge and a high percentage duty cycle. A fixed-gain input amplifier provides a matched input impedance. A method for choosing design specifications provides improved anti-aliasing properties.
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Citations
46 Claims
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1. A wireless communication system, comprising:
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an antenna for receiving and transmitting radio-frequency (RF) signals; frequency conversion circuitry for converting received RF signals into intermediate frequency (IF) signals and for converting output IF signals into transmitted RF signals; an IF transceiver receiving IF signals from and outputting IF signals to said frequency conversion circuitry, said IF transceiver having a receive section including a complex delta-sigma analog-to-digital converter with a loop filter that has real and complex filters cascaded together; and digital signal processing circuitry receiving and processing digital data from said IF transceiver. - View Dependent Claims (2, 3, 4, 5)
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6. An automatic gain control amplifier, comprising:
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a variable gain amplifier having an input and an internal node, having a plurality of discrete selectable gain levels and having negligible phase shift variation between said discrete selectable gain levels; an input impedance connected between said internal node and said input; a feedback impedance connected between said internal node and an output of said amplifier, said plurality of discrete gain levels being dependent upon said feedback impedance and said input impedance; and a variable input compensation impedance connected between said internal node and a common mode voltaie, said variable input compensation impedance combining with said input impedance to maintain constant the impedance seen by said amplifier at said internal node; wherein said amplifier has a constant loop gain over all of said plurality of discrete gain levels; and wherein said input impedance is a variable input impedance and said discrete gain levels are adjusted by varying said variable input impedance. - View Dependent Claims (7)
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8. A variable gain amplifier, comprising:
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an amplifier having an input and an internal node; a feedback impedance connected between said internal node and an output of said amplifier; an input impedance connected between said internal node and said input; said amplifier having a plurality of discrete gain levels dependent upon said feedback impedance and said input impedance and having negligible phase shift variation between said discrete gain levels; and a variable input compensation impedance connected between said internal node and a common mode voltage, said variable input compensation impedance combining with said input impedance to maintain constant the impedance seen by said amplifier at said internal node; wherein said amplifier has a constant loop gain over all of said plurality of discrete gain levels; and wherein said input impedance is a variable input impedance and said discrete gain levels are adjusted by varying said variable input impedance. - View Dependent Claims (9, 10, 11)
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12. A variable gain amplifier, comprising:
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an amplifier having an input and an internal node; a feedback impedance connected between said internal node and an output of said amplifier; an input impedance connected between said internal node and said input; said amplifier having a plurality of discrete gain levels dependent upon said feedback impedance and said input impedance and having negligible phase shift variation between said discrete gain levels; and a variable previous-stage compensation impedance connected between said input and a common mode voltage, said variable previous-stage compensation impedance combining with said input impedance to maintain constant a load impedance seen by previous-stage circuitry; wherein said amplifier has a constant loop gain over all of said plurality of discrete gain levels; and wherein said input impedance is a variable input impedance and said discrete gain levels are adjusted by varying said variable input impedance. - View Dependent Claims (13)
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14. A method for switching between discrete gain level settings in a variable gain amplifier without introducing phase shift variations, comprising:
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providing an amplifier having a plurality of discrete gain level settings defined by a ratio of a variable input impedance to a feedback impedance, said amplifier comprising; an input and an internal node; said feedback impedance connected between said internal node and an output of said amplifier; said variable input impedance connected between said internal node and said input, said discrete gain levels being adjusted by varying said variable input impedance; and a variable input compensation impedance connected between said internal node and a common mode voltage, said variable input compensation impedance combining with said input impedance to maintain constant the impedance seen by said amplifier at said internal node; adjusting said variable input impedance to select one of said plurality of discrete gain level settings; and adjusting a variable input compensation impedance to compensate for changes in said variable input impedance to keep constant a loop gain of said amplifier over all of said discrete gain level settings and to inhibit introduction of phase shift variation between said discrete gain level settings. - View Dependent Claims (15)
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16. Digital clock adjust circuitry, comprising:
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control circuitry receiving a digital clock signal and providing an adjusted clock signal having a first edge produced by allowing a first edge of said digital clock signal to pass through and a second edge triggered by a digital feedback signal; and a feedback network connected between an output and input of said control circuitry to produce said digital feedback signal. - View Dependent Claims (17, 18, 19, 20)
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21. A discrete time sampling circuit, comprising:
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a switched capacitor network connected to an input signal; and clock adjust circuitry receiving a digital clock signal and providing an adjusted clock signal to time said switched capacitor network, said adjusted clock signal having a jitter-free first edge and having a second edge triggered by a feedback signal. - View Dependent Claims (22, 23, 24, 25)
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26. A method for adjusting a digital clock signal, comprising:
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receiving a digital clock signal having a first and second edge within each clock cycle; providing a first jitter-free output edge by passing through said first edge of said digital clock signal; generating a feedback signal from said digital clock signal; and triggering a second output edge based upon said feedback signal, said first jitter-free output edge and said second output edge defining an output clock cycle. - View Dependent Claims (27, 28)
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29. An inverting input amplifier, comprising:
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an amplifier having a finite input impedance at an operating frequency of said amplifier and having a gain that is approximately equal to a ratio of two impedances; and a shunt feedback resistor connected between an input and an output of said amplifier to adjust said finite input impedance to match a desired value; wherein said amplifier is an operational amplifier having a gain set by an input capacitor connected to a negative terminal of said operational amplifier and a feedback capacitor connected between an output of said operational amplifier and said negative terminal. - View Dependent Claims (30)
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31. A low power, matched impedance input amplifier for an intermediate frequency (IF) transceiver, comprising:
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an inverting amplifier with controlled closed loop gain receiving an IF signal from a crystal filter; a shunt feedback resistor connected between an input and an output of said amplifier to adjust said input impedance to match a load impedance desired by said crystal filter; wherein said amplifier is an operational amplifier having a gain set by an input capacitor connected to a negative terminal of said operational amplifier and a feedback capacitor connected between an output of said operational amplifier and said negative terminal.
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32. A method for providing matched impedance amplification with low power requirements for an intermediate frequency (IF) transceiver, comprising:
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providing an inverting amplifier with a controlled closed loop gain receiving an IF signal from a crystal filter; and connecting a shunt feedback resistor between an output and an input of said amplifier to match an input impedance of said amplifier with a load impedance desired by said crystal filter; wherein said providing step includes providing an operational amplifier having a gain set by an input capacitor connected to a negative terminal of said operational amplifier and a feedback capacitor connected between an output of said operational amplifier and said negative terminal.
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33. A method for reducing aliased distortions in a discrete-time sampling receiver, comprising:
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providing a first anti-aliasing filter to receive a signal at an input frequency; providing a limiting amplifier connected to said first anti-aliasing filter; providing a second anti-aliasing filter connected to said limiting amplifier and producing an output that is to be subsequently sampled at a sampling frequency; estimating frequency ranges for potentially interfering distortions; determining rejection of distortions for said first anti-aliasing filter, said limiting amplifier circuitry, and said second anti-aliasing filter in said frequency ranges; adjusting parameters of at least one of said input frequency, said sampling frequency, said first anti-aliasing filter, or said second anti-aliasing filter; and repeating said estimating, said determining and said adjusting steps until said distortion rejection meets a desired level of distortion rejection. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40)
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41. Anti-aliasing circuitry for a discrete-time sampling receiver section of an intermediate frequency (IF) transceiver, comprising:
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a first anti-aliasing filter to receive a signal at an input frequency; a limiting amplifier connected to said first anti-aliasing filter; and a second anti-aliasing filter connected to said limiting amplifier and producing an output that is to be subsequently sampled at a sampling frequency; said input frequency, said sampling frequency, said first anti-aliasing filter, or said second anti-aliasing filter being selected so that rejection of distortion terms meets a desired level of distortion rejection at a desired after-sampling internal signal frequency. - View Dependent Claims (42, 43, 44, 45, 46)
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Specification