System for and method of connecting a hardware modeling element to a hardware modeling system

• US 6,148,275 A
• Filed: 08/28/1997
• Issued: 11/14/2000
• Est. Priority Date: 05/31/1989
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Widdoes, Lawrence Curtis Jr., Mardjuki, Robert Kristianto, Papamarcos, Mark Stanley, Jaeger, Peter Ralph, Read, Andrew Jefferson, Kappauf, William Fitch, Rudin, Melvin, Heideman, Wayne Phillip, Kelly, Norman Francis, Couch, Robert Kimberly
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): JONES, HUGH M
• Application Number:
  US08/919,635
• Time in Patent Office: 1,174 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578, 703/13, 439/490
• US Class Current: 703/13
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: H01R 29/00 Coupling parts for selective co-operation with a counterpart in different ways to establish different circuits, e.g. for voltage selection, for series-parallel selection, programmable connectors
• CPC Class Codes: Y10S 439/955 including electronic identifier or coding means

Abstract

An improved system or and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.

Claims

1. A connector configured for coupling to a hardware modeling system, the connector capable of receiving one of a plurality of electronic devices, wherein each electronic device of the plurality has a different pin-out configuration, wherein the hardware modeling system provides a plurality of electrical signals to an electronic device through the connector and evaluates performance and response of the electronic device, comprising:

a. a grid adapter comprising a matrix of connection pads for coupling to at least one of the electronic devices, wherein at least one of the connection pads is electrically coupled to another one of the connection pads;

b. one or more segments configured for mating to the hardware modeling system, for bi-directionally transmitting electrical signals between the connector and the hardware modeling system, each segment capable of receiving one or more electrical connections from the electronic device;

c. a generation circuit for generating and providing electrical signals to the electronic device through the electrical connections for powering the electronic device; and

d. a memory circuit for storing and providing information to the hardware modeling system regarding predetermined characteristics of the electronic device.

2. The connector as claimed in claim 1 wherein the one or more segments include first, second, and third segments wherein the first segment comprises at least one pin that is longer than pins within the second and third segments and wherein the second segment comprises at least one pin that is longer than pins within the third segment.

3. The connector as claimed in claim 2 further comprising an insertion circuit including electrostatic charge dissipation circuitry coupled to the first segment for first mating with the hardware modeling system when the connector is inserted into the hardware modeling system to dissipate electrostatic charge.

4. The connector as claimed in claim 3 wherein the insertion circuit further includes ground equalization circuitry coupled to the second segment for mating with the hardware modeling system when the connector is inserted and after the electrostatic charge dissipation circuitry to equalize ground levels of the connector, the electronic device and the hardware modeling system.

5. The connector as claimed in claim 4 wherein the insertion circuit further includes power supply control circuitry coupled to the third segment for mating with the hardware modeling system when the connector is inserted and after the electrostatic charge dissipation circuitry and the ground equalization circuitry, to supply power from the hardware modeling system to the connector and the electronic device.

6. The connector as claimed in claim 5 wherein power is supplied from the hardware modeling system to the connector and the electronic device by linearly increasing a power supply voltage input based on a predetermined time constant.

7. The connector as claimed in claim 6 wherein more than one electronic device is coupled to the hardware modeling system at any given time.

8. The connector as claimed in claim 7 wherein the insertion circuit allows the connector to be connected to the hardware modeling system while the hardware modeling system is powered.

9. The connector as claimed in claim 8 wherein the electronic device is a hardware modeling element.

10. The connector as claimed in claim 1 wherein the generation circuit further comprises a voltage regulator coupled to the one or more segments for receiving a first signal from the hardware modeling system for forming a second signal and a switch for selecting one of the first signal and the second signal for powering the electronic device.

11. The connector as claimed in claim 1 further comprising means for refreshing the electronic device when the electronic device is un-accessed for a predetermined period of time.

12. The connector as claimed in claim 1 further comprising an indicator circuit for indicating when the system is powered by the hardware modeling system.

13. The system according to claim 12 wherein the indicator circuit also indicates when the hardware modeling system accesses the electronic device.

14. The connector as claimed in claim 1 wherein the information stored and provided by the memory circuit includes information about the electronic device and a configuration of the connector.

15. The connector as claimed in claim 1 wherein each of the electric signals corresponds to at least one of the connection pads.

16. The connector as claimed in claim 15 wherein the matrix of connection pads is electrically inter-coupled for receiving a plurality of different pin-out configurations for a selected class of electronic device, wherein the class is selected from the following classes of electronic devices:

PGA, DIP, PLCC, and QFP.

17. The connector as claimed in claim 1 wherein a number of connection pads exceeds a number of electrical signals provided by the hardware modeling system.

52. The connector as claimed in claim 1 wherein the one or more segments include first, second, and third segments wherein the first segment comprises at least one first pin that is longer than pins within the second and third segments and wherein the second segment comprises at least one second pin that is longer than pins within the third segment.

53. The connector as claimed in claim 2 further comprising an insertion circuit including electrostatic charge dissipation circuitry coupled to the first segment and configured for first mating with the hardware modeling system when the connector is inserted into the hardware modeling system to dissipate electrostatic charge.

54. The connector as claimed in claim 3 wherein the insertion circuit further includes ground equalization circuitry coupled to the second segment and configured for mating with the hardware modeling system after the electrostatic charge dissipation circuitry is mated with the hardware modeling system and equalizing ground levels of the connector, the selected electronic device and the hardware modeling system.

55. The connector as claimed in claim 4 wherein the insertion circuit further includes power supply control circuitry coupled to the third segment and configured for mating with the hardware modeling system after the electrostatic charge dissipation circuitry and the ground equalization circuitry are mated to the hardware modeling system, and supplying power from the hardware modeling system to the connector and the selected electronic device.

56. The connector as claimed in claim 5 wherein the power supply control circuitry is further configured for supplying the power from the hardware modeling system to the connector and the selected electronic device by linearly increasing a power supply voltage input based on a predetermined time constant.

57. The connector as claimed in claim 6 wherein the connection pad matrix is further configured for receiving a plurality of electronic devices selected from the class of electronic devices at any given time.

58. The connector as claimed in claim 7 wherein the insertion circuit is further configured for allowing the one or more segments to be connected to the hardware modeling system while the hardware modeling system is powered.

59. The connector as claimed in claim 8 wherein the selected electronic device is a hardware modeling element.

60. The connector as claimed in claim 1 wherein the generation circuit further comprises:

(2) a voltage regulator coupled to the one or more segments and configured for receiving a first signal from the hardware modeling system, and forming a second signal; and

(3) a switch coupled to receive the first signal and the second signal and configured for selecting one of the first signal and the second signal for powering the selected electronic device.

61. The connector as claimed in claim 1 further comprising refresh circuitry coupled to the connection pad matrix and configured for refreshing the selected electronic device when the selected electronic device is idle for a predetermined period of time.

62. The connector as claimed in claim 1 further comprising an indicator circuit coupled to the connection pad matrix and configured for indicating when the selected electronic device is powered by the hardware modeling system.

63. The connector according to claim 12 wherein the indicator circuit is further configured for indicating when the hardware modeling system accesses the selected electronic device.

64. The connector as claimed in claim 1 wherein the information stored and provided by the memory circuit further includes information about a configuration of the connector.

65. The connector as claimed in claim 1 wherein each of the input signals provided by the hardware modeling system corresponds to at least one of the plurality of connection pads.

66. The connector as claimed in claim 1 wherein the class of electronic devices is selected from the following classes of electronic devices:

PGA, DIP, PLCC, and QFP.

67. The connector as claimed in claim 1 wherein a number of the plurality of connection pads exceeds a number of the input signals provided by the hardware modeling system.

18. A system for connecting one of a plurality of hardware modeling elements to a hardware modeling system that is capable of evaluating the performance of the hardware modeling element in response to stimuli provided by the hardware modeling system, wherein each hardware modeling element of the plurality has a plurality of signal pins arranged differently from another hardware modeling element of the plurality, comprising:

a. a connector having at least one segment for mating with a section of the hardware modeling system, such that a number of electrical signals can be bi-directionally transmitted between the connector and the hardware modeling system;

b. a grid adapter coupled to the connector and for coupling to the hardware modeling element for providing signals to the hardware modeling element and receiving signals from the hardware modeling element, the grid adapter having a matrix of connection pads for receiving the plurality of signal pins of the hardware modeling element wherein a first connection pad is electrically coupled to a second connection pad;

c. a generation circuit for generating and providing electrical signals to the hardware modeling element; and

d. a memory circuit for storing and providing information to the hardware modeling system regarding predetermined characteristics of the hardware modeling element.

19. The system as claimed in claim 18 wherein the connector comprises first, second and third segments, wherein the first segment includes a first pin longer than a second pin within the second segment and longer than a third pin within the third segment, wherein the second pin is longer than the third pin.

20. The system as claimed in claim 19 further comprising an insertion circuit including electrostatic charge dissipation circuitry coupled to the first segment for mating with the hardware modeling system when the connector is first inserted into the hardware modeling system to dissipate electrostatic charge.

21. The system as claimed in claim 20 wherein the insertion circuit further includes ground equalization circuitry coupled to the second segment for mating with the hardware modeling system when the connector is inserted and after the electrostatic charge dissipation circuitry to equalize ground levels of the connector, the hardware modeling element and the hardware modeling system.

22. The system as claimed in claim 21 wherein the insertion circuit further includes power supply control circuitry coupled to the third segment for mating with the hardware modeling system when the connector is inserted and after the electrostatic charge dissipation circuitry and the ground equalization circuitry to supply power from the hardware modeling system to the connector and the hardware modeling element.

23. The system as claimed in claim 22 wherein the insertion circuit is further configured for supplying the power from the hardware modeling system to the connector and the hardware modeling element by linearly increasing a power supply voltage input based on a predetermined time constant.

24. The system as claimed in claim 23 wherein the insertion circuit allows the connector to be connected to the hardware modeling system while the hardware modeling system is powered.

25. The system as claimed in claim 24 wherein the generation circuit further comprises a voltage regulator coupled to the one or more segments for receiving a first signal from the hardware modeling system for forming a second signal and a switch for selecting one of the first signal and the second signal for powering the hardware modeling element.

26. The system as claimed in claim 25 further comprising a refreshing circuit for refreshing the hardware modeling element if the hardware modeling element is not accessed by the hardware modeling system for a predetermined period of time.

28. The system as claimed in claim 18 wherein a number of connection pads exceeds the number of electrical signals that can be bi-directionally transmitted between the connector and the hardware modeling system.

29. The system as claimed in claim 18 wherein the connection pads are arranged in concentric rectangular rings for accepting electronic devices having PGA pin-out package configurations.

30. The system as claimed in claim 29 wherein a first concentric rectangular ring comprises the first connection pad and a second concentric rectangular ring comprises the second connection pad.

31. The system as claimed in claim 18 wherein the connection pads are arranged in parallel rows for accepting electronic devices of different sizes having DIP pin-out package configurations.

32. The system as claimed in claim 31 wherein each of the connection pads of at least one parallel row is electrically coupled to a corresponding one of the connection pads of at least one other of the parallel rows.

33. The system as claimed in claim 18 wherein the connection pads are arranged in a first rectangular ring and a second rectangular ring, the first rectangular ring comprising 28 connection pads for accepting a first electronic device having a 28-pins PLCC pin-out package configuration, the second rectangular ring comprising 20 connection pads for accepting a second electronic device having a 20-pins PLCC pin-out package configuration, wherein the first rectangular ring and the second rectangular ring share at least two common pads.

34. The system as claimed in claim 33 wherein at least one of the connection pads of the first rectangular ring is electrically coupled to at least one of the connection pads of a side of the second rectangular ring.

27. A hardware modeling system for simulating a circuit and providing signals to and measuring responses from a hardware modeling element comprising:

a. a connector capable of being inserted to the hardware modeling system while the hardware modeling system is powered including;

i. electrostatic charge dissipation circuitry to dissipate electrostatic charge;

ii. a first segment including a first pin of a first length coupled to the electrostatic charge dissipation circuitry;

iii. ground equalization circuitry to equalize ground levels of the connector, the hardware modeling system and the hardware modeling element;

iv. a second segment including a second pin of a second length coupled to the ground equalization circuitry;

v. power supply control circuitry to supply power from the hardware modeling system to the connector and the hardware modeling element;

vi. a third segment including a third pin of a third length coupled to the power supply control circuitry;

wherein the first length is longer than the second and third lengths and the second length is longer than the third length such that when the connector is inserted into the hardware modeling system, the first pin engages the hardware modeling system first, the second pin engages the hardware modeling system second and the third pin engages the hardware modeling system third;

b. a grid adapter coupled to the connector and configured to receive the hardware modeling element for providing signals to the hardware modeling element and receiving signals from the hardware modeling element, the grid adapter comprising a matrix of connection pads arranged in concentric rectangular rings adapted for receiving one of a plurality of hardware modeling elements each having a different pin-out configuration, wherein at least one of the connection pads is electrically coupled to another one of the connection pads;

c. a generation circuit for generating and providing electrical signals to the hardware modeling element including a voltage regulator coupled to the connector for receiving a first signal and forming a second signal, and a switch for selecting between a selective one of the first signal and the second signal for powering the hardware modeling element; and

d. a memory circuit for storing and providing information to the hardware modeling system regarding predetermined characteristics of the hardware modeling element.

35. A device adapter circuit board for interfacing between a hardware modeling system and one of a plurality of integrated circuits, wherein each integrated circuit of the plurality has a different footprint, comprising:

a. a plurality of system connectors, each system connector having a plurality of signal lines coupled to the hardware modeling system for bi-directionally transmitting electrical signals between the hardware modeling system and the integrated circuit, wherein a total number of signal lines is not smaller than a number of pins of the integrated circuit; and

b. a footprint adapter having a plurality of connection pads for coupling to the integrated circuit, wherein each signal line is electrically coupled to at least one connection pad, further wherein a number of connection pads exceeds the number of pins of the integrated circuit.

36. The device adapter circuit board as claimed in claim 35, wherein the connection pads are arranged in concentric rectangular rings for accepting PGA integrated circuits having different numbers of pins and pin-out configurations.

37. The device adapter circuit board as claimed in claim 36, wherein the concentric rectangular rings comprise an outer ring and an inner ring, further wherein at least one connection pad of the outer ring is electrically coupled to at least one connection pad of the inner ring.

38. The device adapter circuit board as claimed in claim 35, wherein the connection pads are arranged in a plurality of parallel rows for accepting integrated circuits having DIP pin-out package configuration and having different numbers of pins, wherein each connection pad in a first row is aligned directly across from a corresponding connection pad in a second row.

39. The device adapter circuit board as claimed in claim 38, wherein at least one connection pad of the first row is electrically coupled to at least one connection pad of the second row.

40. The device adapter circuit board as claimed in claim 35, wherein the connection pads are arranged in a first rectangular ring and a second rectangular ring, the first rectangular ring having 28 connection pads for accepting an electronic device having a 28-pins PLCC pin-out package configuration, the second rectangular ring having 20 connection pads for accepting an electronic device having a 20-pins PLCC pin-out package configuration, wherein the first rectangular ring and the second rectangular ring share at least two common pads.

41. The device adapter circuit board as claimed in claim 40 wherein at least one of the connection pads of a side of the first rectangular ring is electrically coupled to at least one of the connection pads of a side of the second rectangular ring.

42. A method of providing electrical connections between a hardware modeler and hardware modeling elements having different footprint dimensions, the method comprising the steps of:

a. providing a two-dimensional array of connector sockets;

b. identifying a first plurality of the connector sockets corresponding to a first footprint dimension;

c. connecting each of the first plurality of connector sockets to the hardware modeler;

d. identifying a second plurality of the connector sockets corresponding to a second footprint dimension, wherein the second plurality includes a subset of the first plurality; and

e. connecting each of the second plurality of connector sockets excluded by the subset to each of the first plurality of the connector sockets excluded by the subset, whereby each of the second plurality of the connector sockets are electrically coupled to the hardware modeler.

43. The method according to claim 42 wherein the hardware modeling elements belong to a same class of pin-out configurations.

44. The method according to claim 43 further comprising the step of repeating the steps b-e for other footprint dimensions within the same class of pin-out configurations.

45. The method according to claim 42 wherein the hardware modeling elements have a 240 pin PGA pin-out configuration.

46. An adapter circuit board for providing electrical connections between hardware modeling elements having a different footprint dimensions and a hardware modeler, the adapter circuit board comprising:

a. a first plurality of connector sockets configured for receiving hardware modeling elements having a first footprint dimension, wherein each of the first plurality of connector sockets is configured for connecting to the hardware modeler;

b. a second plurality of connector sockets configured for receiving hardware modeling elements having a second footprint dimension, wherein the second plurality of connector sockets include a subset of the first plurality of connector sockets, further wherein the second plurality of connector sockets excluded by the subset are electrically coupled to the first plurality of connector sockets excluded by the subset, whereby the second plurality of connector sockets are electrically coupled to the hardware modeler.

47. The adapter circuit board according to claim 46 wherein the adapter circuit board is configured to receive hardware modeling elements belonging to a same class of pin-out configurations.

48. The adapter circuit board according to claim 46 wherein the adapter circuit board is configured to receive hardware modeling elements having a 240 pin PGA pin-out configuration arranged in different footprint dimensions.

49. The adapter circuit board according to claim 46 further comprising a connector for coupling to the hardware modeler.

50. The adapter circuit board according to claim 49 wherein the connector further comprises an insertion circuit including electrostatic charge dissipation circuitry configured to effect first contact with the hardware modeler during mating, ground equalization circuitry configured to effect second contact with the hardware modeler, and power supply circuitry configured to effect third contact with the hardware modeler.

68. The adapter circuit board according to claim 46 further comprising a connector coupled to the first plurality of connector sockets and configured for coupling to the hardware modeler.

69. The adapter circuit board according to claim 49 further comprising an insertion circuit coupled to the connector and including electrostatic charge dissipation circuitry configured to effect first contact with the hardware modeler during mating, ground equalization circuitry configured to effect second contact with the hardware modeler, and power supply circuit configured to effect third contact with the hardware modeler.

51. A connector capable of coupling to each of a class of electronic devices wherein each of the class of electronic devices has a different pin-out configuration, the connector configured for receiving input signals from a hardware modeling system, coupling to a selected electronic device from the class of electronic devices wherein the selected electronic device has a selected pin-out configuration, providing the input signals from the hardware modeling system to the selected electronic device, receiving a device signal from the selected electronic device and providing the device signal to the hardware modeling system for evaluating performance and response of the selected electronic device, the connector comprising:

a. a connection pad matrix including;

(a) a plurality of connection pads configured for coupling to the different pin-out configurations of the class of electronic devices, wherein the plurality of connection pads includes a plurality of footprint pads configured for mating with the selected pin-out configuration and receiving the device signal from the selected electronic device;

(b) one or more segments configured for mating with the hardware modeling system, receiving the input signals and bi-directionally transmitting electrical signals between the selected electronic device and the hardware modeling system, wherein each segment is configured for receiving one or more electrical connections from the selected electronic device;

b. a grid adaptor coupled to the connection pad matrix and configured for electrically coupling at least one of the plurality of connection pads to another of the plurality of connection pads such that each of the plurality of footprint pads is coupled to a corresponding one of the one or more segments thereby configuring the plurality of connection pads for mating with the selected pin-out configuration;

c. a generation circuit coupled to the connection pad matrix and configured for generating and providing a power signal to the selected electronic device through the electrical connections; and

d. a memory circuit coupled to the connection pad matrix and configured for storing information regarding predetermined characteristics of the selected electronic device and providing the information to the hardware modeling system.