Method and apparatus for cascading content addressable memory devices
First Claim
1. A content addressable memory (CAM) device comprising:
- a CAM circuit for storing data;
data inputs for providing comparand data for comparison with the data of the CAM circuit;
a cascade circuit coupled to the CAM circuit;
a match flag output coupled to the cascade circuit, the match flag output for providing a match flag output signal indicative of whether the comparand data matches the data of the CAM circuit; and
a cascade output coupled to the cascade circuit, the cascade output for providing a cascade output signal indicative of when the match flag output signal is valid.
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Accused Products
Abstract
A method and apparatus for cascading content addressable memory (CAM) devices is disclosed. The method and apparatus may be particularly useful when depth cascading CAM devices that operate in a flow-through mode. In the flow-through mode, a compare instruction may be simultaneously provided to each CAM device in the cascade, and the match address, data stored at the matched location, or other status information may then be output to a common output data bus by the highest priority matching CAM device in the same cycle that the instruction is provided to the CAM devices. Each CAM device may have a cascade input and a cascade output to perform the cascade function. The cascade output of a higher priority CAM device may be connected to the cascade input of the next lower priority CAM device. The higher priority CAM device may assert a cascade signal on its cascade output at a predetermined time after receiving an input signal (e.g., a clock signal). Asserting the cascade signal may indicate that the higher priority CAM device has completed the compare instruction. When the lower priority CAM device detects that the cascade signal has been asserted on its cascade input, the lower priority CAM device may sample the match flag of the higher priority CAM device to determine if the lower priority CAM device may output its data to the common output data bus.
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Citations
31 Claims
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1. A content addressable memory (CAM) device comprising:
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a CAM circuit for storing data; data inputs for providing comparand data for comparison with the data of the CAM circuit; a cascade circuit coupled to the CAM circuit; a match flag output coupled to the cascade circuit, the match flag output for providing a match flag output signal indicative of whether the comparand data matches the data of the CAM circuit; and a cascade output coupled to the cascade circuit, the cascade output for providing a cascade output signal indicative of when the match flag output signal is valid. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A content addressable memory (CAM) device comprising:
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a CAM circuit for storing data; data inputs for providing comparand data for comparison with the data of the CAM circuit, a cascade circuit coupled to the CAM circuit; a match flag input coupled to the cascade circuit, the match flag input for receiving a match flag input signal from another CAM device; and a cascade out coupled to the cascade circuit, the cascade input for receiving a cascade input signal from the other CAM device indicative of when the match flag input signal from the other CAM device is valid. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A system comprising:
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a first content addressable memory (CAM) device having a cascade output and a match flag output, the match flag output for providing a match flag output signal indicative of whether comparand data matches data of the first CAM device, the cascade output for providing a cascade output signal indicative of when the match flag output signal is valid; and a second content addressable memory (CAM) device coupled in a depth cascade configuration with the first CAM device, the second CAM device having a cascade input, a match flag input, and a cascade output, the cascade input of the second CAM device coupled to the cascade output of the first CAM device, the match flag input of the second CAM device coupled to the match flag output of the first CAM device. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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26. A method of depth cascading first and second content addressable memory (CAM) devices comprising:
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instructing the first and second CAM devices to execute a compare operation between comparand data and first data stored in the first CAM device and second data stored in the second CAM device; providing a match flag signal from the first CAM device to the second CAM device, the match flag signal indicating whether the comparand data matches the first data; and providing a cascade output signal from the first CAM device to the second CAM device, the cascade output signal indicating when the the match flag signal is valid for sampling by the second CAM device. - View Dependent Claims (27, 28, 29, 30)
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31. A method of operating a content addressable memory (CAM) device comprising:
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instructing the CAM device to execute a compare operation between comparand data and data stored in the CAM device; generating a match flag signal from the CAM device, the match flag signal indicatative of whether the comparand data matches the data stored in the CAM device; and generating an output signal from the CAM device, the output signal indicating when the the match flag signal is valid.
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Specification