Flash EEprom system

• US 6,149,316 A
• Filed: 01/29/1997
• Issued: 11/21/2000
• Est. Priority Date: 04/13/1989
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): HUA, LY
• Application Number:
  US08/789,421
• Time in Patent Office: 1,392 Days
• Field of Search: 395/182.06, 395/430, 395/182.05, 365/218, 365/185.33, 365/185.18, 371/10.2
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A method of operating a bulk storage memory with a host processor, wherein the bulk storage memory includes an array of non-volatile floating gate memory cells, comprising:

storing, within defined non-overlapping groups of array cells that are erasable together as a unit, user data and associated overhead data, at least some of said overhead data being generated within the bulk storage memory to include information of the same individual memory array cell groups in which the overhead data are stored

in response to receipt from the host processor of an address in a format designating at least one mass memory storage block address, converting said at least one mass memory storage block address into an address of at least one of the memory array cell groups and addressing said at least one of the memory array cell groups,

in response to receipt from the host processor of user data and a command to write said user data to said at least one mass memory storage block address, writing said user data into the addressed at least one of the memory array cell groups, and

in response to receipt from the host processor of a command to read user data from said at least one mass memory storage block address, reading said user data and associated overhead data from the addressed at least one of the memory array cell groups.

2. The method according to claim 1, wherein, in response to receipt from the host processor of the command to write user data, reading and processing the overhead data stored in the addressed at least one of the groups of array cells prior to writing the user data into said addressed at least one of the groups of array cells.

3. The method according to claim 1, wherein, in response to receipt from the host processor of a command to read user data, first processing the overhead data associated with the user data stored in the addressed at least one of the groups of array cells.

4. The method according to claim 1, additionally comprising:

detecting a predefined condition when individual ones of the groups of array cells become unusable and linking the addresses of such unusable groups with addresses of other groups of array cells that are useable, and

wherein addressing said at least one of the groups of array cells includes referring to the linked address of another group that is usable and then mapping said at least one mass memory storage block address into such another group.

5. The method according to claim 4, wherein detecting of the predefined condition includes detecting when individual groups of array cells have become defective.

6. The method according to claim 5, wherein detecting when individual groups of array cells become defective includes determining when a number of individual defective memory cells within a group exceed a given number.

7. The method according to claim 4, wherein linking the address of unusable groups of array cells with groups that are useable includes maintaining a list that links such unusable groups with addresses of corresponding ones of other groups that are useable, and wherein addressing a usable group includes referring to the list to translate the address of the unusable group into an address of a usable group.

8. The method according to claim 4, wherein linking the address of such unusable groups includes storing within individual ones of the defective groups addresses of corresponding useable groups, and wherein addressing a usable group corresponding to an unusable group includes referring to the useable group address stored in the unusable group.

9. The method according to any one of claims 1-3, wherein the overhead data stored within the addressed at least one of the groups of array cells includes the address of the group in which the overhead data are stored.

10. The method according to claim 9, wherein storing data includes programming the individual memory cells of the array into one of exactly two programmable states in order to store exactly one bit of data per cell.

11. The method according to claim 9, wherein storing data includes programming the individual memory cells of the array into one of more than two programmable states in order to store more than one bit of data per cell.

12. The method according to any one of claims 1-3 or 4-8, wherein the mass memory storage block address is a magnetic disk sector.

13. The method according to claim 12, wherein the mass memory storage block address includes designation of a magnetic disk drive head, cylinder and sector.

14. The method according to claim 12, wherein storing data includes programming the individual memory cells of the array into one of exactly two programmable states in order to store exactly one bit of data per cell.

15. The method according to claim 12, wherein storing data includes programming the individual memory cells of the array into one of more than two programmable states in order to store more than one bit of data per cell.

16. The method according to any one of claims 1-3 or 7-11, wherein the amount of user data stored in individual ones of the groups of array cells is substantially the same as the amount of user data contained in individual ones of individual mass memory storage blocks of data transferred between the bulk storage memory and the host processor.

17. The method according to claim 16, wherein said amount of user data is substantially 512 bytes.

18. The method according to claim 16, wherein said bulk storage memory is provided within a single card that is removably connectable to the host processor through an electrical connector.

19. The method according to claim 16, further comprising erasing data from a selected at least one of the individual groups of array cells by simultaneously applying an erase voltage to all of the cells within said selected at least one group, thereby to simultaneously erase any user data and associated overhead data contained in said at least one group of cells.

20. The method according to claim 16, wherein storing data includes programming the individual memory cells of the array into one of exactly two programmable states in order to store exactly one bit of data per cell.

21. The method according to claim 16, wherein storing data includes programming the individual memory cells of the array into one of more than two programmable states in order to store more than one bit of data per cell.

22. The method according to any one of claims 1-3 or 4-8, wherein said bulk storage memory is implemented in a single package.

23. The method according to claim 22, wherein said bulk storage memory is provided within a card that is removably connectable to the host processor through an electrical connector.

24. The method according to claim 23, wherein storing data includes programming the individual memory cells of the array into one of exactly two programmable states in order to store exactly one bit of data per cell.

25. The method according to claim 23, wherein storing data includes programming the individual memory cells of the array into one of more than two programmable states in order to store more than one bit of data per cell.

26. The method according to any one of claims 1-3 or 4-8, further comprising erasing data from a selected at least one of the individual groups of array cells by simultaneously applying an erase voltage to all of the cells within said selected at least one group, thereby to simultaneously erase any user data and associated overhead data contained in said at least one group of cells.

27. The method according to claim 26, wherein the memory array cells individually include erase gates, and the erase voltage is simultaneously applied to the erase gates of said selected at least one group of array cells.

28. The method according to claim 26, wherein storing data includes programming the individual memory cells of the array into one of exactly two programmable states in order to store exactly one bit of data per cell.

29. The method according to claim 26, wherein storing data includes programming the individual memory cells of the array into one of more than two programmable states in order to store more than one bit of data per cell.

30. The method according to any one of claims 1-3 or 4-8, wherein storing data includes programming the individual memory cells of the array into one of exactly two programmable states in order to store exactly one bit of data per cell.

31. The method according to any one of claims 1-3 or 4-8, wherein storing data includes programming the individual memory cells of the array into one of more than two programmable states in order to store more than one bit of data per cell.

32. A bulk storage memory system that is connectable to a host computer system, said memory system comprising:

an array of non-volatile floating gate memory cells arranged to store in designated blocks thereof a given amount of user data and associated overhead data, and

a controller connectable to said computer system for controlling operation of the array, said controller including;

an addressing circuit responsive to receipt of a mass memory storage block address from the host computer system to address a corresponding array block of user data and associated overhead data,

a reading circuit responsive to the addressing circuit to read the associated overhead data of the addressed array block, and

a data transfer circuit responsive to the addressing circuit and the read overhead data to execute an instruction from the host computer system to perform a designated one of reading user data from, or writing user data to, the addressed array block.

33. The memory system according to claim 32 additionally comprising a list of any of said blocks that are unusable that link said unusable blocks with others of said blocks that are usable, and wherein said addressing circuit includes a circuit to access linked others of said blocks in place of said unusable blocks.

34. The memory system according to claim 33 wherein the list of unusable blocks includes a list maintained within the bulk storage memory system outside of blocks of the memory array designated to store user data and associated overhead data.

35. The memory system according to claim 33 wherein the list of unusable blocks includes a list stored as part of the overhead data associated with the unusable blocks.

36. The memory system according to any one of claims 33-35 wherein the list of any unusable blocks includes inoperable or defective blocks .

37. The memory system according to any one of claims 33-35 wherein the list of any unusable blocks includes blocks that contain a number of defective cells in excess of a preset number.

38. The memory system according to any one of claims 32-35 wherein said given amount of user data is substantially 512 bytes.

39. The memory system according to any one of claims 32-35 wherein said mass memory storage block address is a magnetic disk sector address.

40. The memory system according to claim 39 wherein said magnetic disk sector address includes a head, cylinder and sector.

41. The memory system according to claim 39, wherein the cells of the array are individually programmable into exactly two states in order to store exactly one bit of data per cell.

42. The memory system according to claim 39, wherein the cells of the array are individually programmable into more than two states in order to store more than one bit of data per cell.

43. The memory system according to any one of claims 32-35, wherein said bulk storage memory system is implemented in a single package.

44. The memory system according to claim 43, wherein said bulk storage memory system is provided within a card that is removably connectable to the computer system through an electrical connector.

45. The memory system according to claim 44, wherein the cells of the array are individually programmable into exactly two states in order to store exactly one bit of data per cell.

46. The memory system according to claim 44, wherein the cells of the array are individually programmable into more than two states in order to store more than one bit of data per cell.

47. The memory system according to any one of claims 32-35, wherein the data transfer circuit additionally transfers user data in parallel to and from the host computer system.

48. The memory system according to any one of claims 32-35, additionally comprising an erasing circuit that simultaneously erases the memory cells within individual designated array blocks to simultaneously erase any user data and associated overhead data stored therein.

49. The memory system according to claim 48, wherein the cells of the array are individually programmable into exactly two states in order to store exactly one bit of data per cell.

50. The memory system according to claim 48, wherein the cells of the array are individually programmable into more than two states in order to store more than one bit of data per cell.

51. The memory system according to any one of claims 32-35, wherein the cells of the array are individually programmable into exactly two states in order to store exactly one bit of data per cell.

52. The memory system according to any one of claims 32-35, wherein the cells of the array are individually programmable into more than two states in order to store more than one bit of data per cell.

53. A method of operating a memory system with a host system that includes a processor, wherein the memory system includes one or more integrated circuit chips individually including an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

providing said one or more chips and a memory controller within a card that is removably connectable to the host system, said controller being connectable to said processor for controlling operation of the memory system when the card is connected to the host system,

operating the memory cells within the individual sectors with at least a user data portion and an overhead portion,

detecting a predefined condition when individual sectors become unusable and linking the addresses of such unusable sectors with addresses of other sectors that are useable,

causing the controller, in response to receipt from the processor of an address in a format designating at least one mass memory storage block, to generate an address of a non-volatile memory sector that corresponds to said at least one mass memory storage block,

accessing a usable sector of the memory system, if the sector with the generated address is unusable, by referring to the linked address of another sector that is usable and then accessing that other sector,

either writing data to, or reading data from, the user data portion of the accessed usable sector, and

either writing to, or reading from, said overhead portion of the accessed usable sector, information related to either the accessed usable sector or data stored in the user data portion of said accessed useful sector.

54. The method according to claim 53, wherein the detecting of the predefined condition includes detecting when individual sectors become defective.

55. The method according to claim 54, wherein the detecting of when individual sectors become defective includes determining when a number of individual defective memory cells within a sector exceed a given number.

56. The method according to claim 53, wherein the user data portion of the individual non-volatile memory sectors has a capacity of substantially 512 bytes.

57. The method according to claim 53, wherein the information stored in the overhead portion of the individual sectors includes an address of the respective ones of the individual sectors.

58. The method according to claim 53, wherein the information stored in the overhead portion of the individual sectors includes an error correction code calculated from data stored in the user data portions of corresponding ones of the individual sectors.

59. The method according to claim 53 wherein linking the address of unusable sectors with sectors that are useable includes maintaining a list within the card that links such unusable sectors with addresses of corresponding ones of the other sectors that are useable, and wherein accessing a usable sector includes referring to the list to translate the address of the unusable sector into an address of a usable sector.

60. The method according to claim 53 wherein linking the address of such unusable sectors includes storing within individual ones of the defective sectors addresses of corresponding useable sectors, and wherein accessing a usable sector corresponding to an unusable sector includes referring to the useable sector address stored in the unusable sector.

61. The method according to claim 53, wherein causing the controller to generate an address of a non-volatile memory sector includes doing so for a non-volatile memory sector that corresponds to only one mass memory storage block, wherein the user data portion of the individual non-volatile memory sectors has a capacity that is substantially the same as a user data portion of said one mass memory storage block.

62. The method of any of claims 53-61, wherein writing to the accessed usable sector includes programming the individual memory cells thereof into exactly two programmable states in order to store exactly one bit of data or information per cell.

63. The method of claim 62, wherein the address of said at least one mass memory storage block is an address of at least one magnetic disk sector.

64. The memory of any one of claims 53-61, wherein writing to the accessed usable sector includes programming the individual memory cells thereof into one of more than two programmable states in order to store more than one bit of data information per cell.

65. The method of claim 64, wherein the address of said at least one mass memory storage block is an address of at least one magnetic disk sector.

66. The method any one of claims 53-61, wherein communication of mass memory storage block addresses and user data with the controller is in parallel over a bus.

67. A method of operating a memory system with a host system that includes a processor, wherein the memory system includes one or more integrated circuit chips individually including an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

providing said one or more chips and a memory controller within a card that is removably connectable to the host system, said controller being connectable to said processor for controlling operation of the memory system when the card is connected to the host system,

operating the memory cells within the individual sectors with at least a user data portion and an overhead portion,

causing the controller, in response to receipt from the processor of an address in a format designating at least one mass memory storage block, to designate an address of at least one non-volatile memory sector that corresponds with said at least one mass memory storage block,

either writing user data to, or reading from, the user data portion of said at least one non-volatile memory sector, and

either writing to, or reading from, said overhead portion of said at least one non-volatile memory sector, overhead data related either to said at least one non-volatile memory sector or to data stored in the user data portion of said at least one non-volatile memory sector.

68. The method of claim 67, wherein the user data portion of the individual sectors has a capacity of substantially 512 bytes.

69. The method of claim 67, wherein the overhead data stored in said overhead portion of the individual sectors includes addresses of the individual sectors.

70. The method of claim 67, wherein partitioning the memory cells includes partitioning said memory cells within the individual sectors to include an additional portion spare memory cells.

71. The method of claim 70, wherein the overhead data stored in said overhead portion of the individual sectors includes an identification of any defective cells within the user data portion of corresponding ones of said sectors, said method additionally comprising causing the controller to read the identification of defective cells from the overhead portion of said addressed at least one non-volatile memory sector and then to substitute therefore other cells within the spare cell portion of the addressed at least one non-volatile memory sector.

72. The method of claim 67, additionally comprising causing the controller to identify and store addresses of any defective non-volatile memory sectors within the array, and, wherein designating an address of a sector includes, in response to designating an address of a defective sector, substituting an address of another sector instead.

73. The method of claim 67, wherein the individual sectors include only one user data portion and only one overhead data portion.

74. The method of any one of claims 67-73, wherein writing to said at least one non-volatile memory sector includes programming the individual memory cells thereof into one of exactly two programmable states in order to store exactly one bit of data per cell.

75. The method of claim 74, wherein the address of said at least one mass memory storage block is an address of at least one magnetic disk sector.

76. The method of any one of claims 67-73, wherein writing to said at least one non-volatile memory sector includes programming the individual memory cells thereof into one of more than two programmable states in order to store more than one bit of data per cell.

77. The method of claim 76, wherein the address of said at least one mass memory storage block is an address of at least one magnetic disk sector.

78. The method any one of claims 67-73, wherein communication of mass memory storage block addresses and user data with the controller is in parallel over a bus.

79. A memory system connectable to a host processor to enable the exchange of data therebetween, and memory system comprising:

an array of non-volatile floating gate memory cells partitioned into a plurality of blocks of cells that individually store a given amount of user data and overhead data, wherein the memory cells are individually programmable into one of more than two distinct threshold level ranges corresponding to more than one bit of data per cell, and

a controller connected to the array and removably connectable to the host through an electrical connector, said controller including;

an address generator that is responsive to receipt of a mass memory storage block address from the host to address a corresponding at least one of the plurality of memory blocks, and

a data transfer control that responds to an instruction from the host to perform a disignated one of reading user data from, or writing user data to, said at least one address block, including a data writing circuit that generates at least some of the overhead data associated with at least one of at least one addressed block or user data being written therein, and a data reading circuit that reads the overhead data from said at least one addressed block, wherein the data writing circuit programs the individual memory cells into said one of more than two distinct threshold level ranges and the data reading circuit reads one of more than two distinct threshold level ranges from the individual memory cells.

80. The memory system according to claim 79 additionally comprising a list of any of said memory blocks that are unusable that link said unusable blocks with others of said blocks that are usable, and wherein said addressing circuit includes a circuit to access linked others of said blocks in place of said unusable blocks.

81. The memory system according to claim 80 wherein the list of unusable blocks includes a list maintained within the bulk storage memory system outside of blocks of the memory array designated to store user and overhead data.

82. The memory system according to claim 80 wherein the list of unusable blocks includes a list stored as part of the overhead data associated with unusable memory array blocks.

83. The memory system according to any one of claims 80-82 wherein the list of any unusable blocks includes inoperable or defective blocks.

84. The memory system according to any one of claims 80-82 wherein the list of any unusable blocks includes blocks that contain a number of defective cells in excess of a preset number.

85. The memory system according to any one of claims 79-82 wherein the list given amount of user data is substantially 512 bytes.

86. The memory system according to any one of claims 79-82 wherein said mass memory storage block address is a magnetic disk sector address.

87. The memory system according to claim 80 wherein said magnetic disk sector address includes a head, cylinder and sector.

88. The memory system according to any one of claims 79-82 wherein said bulk storage memory system is implemented in a single package.

89. The memory system according to any one of claim 88 wherein said bulk storage memory system is provided within a card that is removably connectable to the computer system through said electrical connector.

90. The memory system according to any one of claim 89 wherein the cells of the array are individually programmable into exactly two states in order to store exactly one bit of data per cell.

91. The memory system according to any one of claim 89 wherein the cells of the array are individually programmable into more than two states in order to store more than one bit of data per cell.

92. The memory system according to any one of claims 79-82, wherein the data transfer control additionally transfers the user data in parallel to and from the host.

93. The memory system according to any one of claims 79-82, additionally comprising an erasing circuit that simultaneously erases the individual cells within individual designated blocks.

94. The memory system according to claim 93, wherein the overhead data generated in the data transfer control and written into said at least one addressed block includes at least one of a group of an error correction code for the user data written into said at least one addressed block, an address of the individual said at least one addressed block, a map of defective cells within said at least one addressed block and a count related to a number of times that said at least one addressed block has been erased.

95. The memory system according to claim 93, wherein the cells of the array are individually programmable into exactly two states in order to store exactly one bit of data per cell.

96. The memory system according to claim 93, wherein the cells of the array are individually programmable into more than two states in order to store more than one bit of data per cell.

97. The memory system according to any one of claims 79-82, wherein the cells of the array are individually programmable into exactly two states in order to store exactly one bit of data per cell.

98. The memory system according to any one of claims 79-82, wherein the cells of the array are individually programmable into more than two states in order to store more than one bit of data per cell.

99. A method of operating, with a host processor, a non-volatile memory system that includes an array of non-volatile floating gate memory cells partitioned into sectors of memory cells that are erasable together as a unit, comprising:

providing said memory array and a memory controller within a card that is removably connectable to the host processor, the controller being connectable to said host processor for controlling operation of the memory array when the card is connected to the host processor, and the memory cells within said memory array being individual programmable into one or more than two distinct threshold level ranges corresponding to more than one bit of data per cell,

causing the controller, in response to receipt from the host processor of an address in a format designating at least one mass memory storage sector, to designate an address of at least one non-volatile memory sector that corresponds with said at least one mass memory storage block,

either writing user data to, or reading user data from, said at least one non-volatile memory sector,

either writing to, or reading from, said at least one non-volatile memory sector, overhead data related either to said at least one non-volatile memory sector or to user data stored in said at least one non-volatile memory sector, and

wherein the writint of user and overhead data includes programming the individual memory cells of the array into said one of more than two distinct threshold level ranges.

100. The method of claim 99, wherein the overhead data written into said at least one non-volatile memory sector is generaged within the memory controller.

101. The method of claim 99, wherein the user data written into the individual sectors is substantially 512 bytes.

102. The method of claim 99, wherein the overhead data stored in said overhead portion of the individual sectors includes addresses of the individual sectors.

103. The method of claim 102, wherein the overhead data stored in said overhead portion of the individual sectors additionally includes, in those sectors that are defective, addresses of sectors being substituted therefor.

104. The method of claim 99, additionally comprising causing the controller to identify and store addresses of any defective non-volatile memory sectors within the array, and, wherein designating an address of said at least one memory sector includes, in response to designating an address of a defective sector, substituting an address of another sector instead.

105. The method of claim 99, wherein the address of said at least one mass memory storage block includes an address of at least one magnetic disk sector.

106. The method of claim 99, further comprising erasing data from a selected at least one of the individual sectors of memory cells by simultaneously applying an erase voltage to all of the memory cells within said selected at least one sector, thereby to simultaneously erase any user data and associated overhead data contained in said at least one sector.

107. The method of claim 106, wherein the memory array cells individually include erase gates, and the erase voltage is simultaneously applied to the erase gates of said selected at least one sector memory cells.