Semiconductor apparatus having high withstand voltage

• US 6,150,697 A
• Filed: 04/29/1999
• Issued: 11/21/2000
• Est. Priority Date: 04/30/1998
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Abe, Ryuichirou, Teshigahara, Akihiko, Asai, Akiyoshi, Itou, Hiroyasu, Sakakibara, Toshio, Onoda, Kunihiro
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/301,562
• Time in Patent Office: 572 Days
• Field of Search: 257/347, 257/348, 257/335, 257/336
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

An island region surrounded by a trench is provided in an SOI substrate. The island region is further surrounded by a buffer region with a buffer region contact layer. In the island region, a source region is annularly provided around a drain region, and source and drain electrodes are respectively provided on the source and the drain regions. An annular auxiliary electrode is formed with the source electrode to extend over the trench. Accordingly, a voltage applied to the source electrode can be applied to the auxiliary electrode, so that electric field concentration between the buffer region and the source electrode is relaxed.

Claims

1. A semiconductor apparatus comprising:

a support substrate;

an insulation layer provided on the support substrate;

a semiconductor layer provided on the insulation layer and including a first element formation region and a second element formation region as an island region that is surrounded by a trench region to be electrically isolated from the first element formation region;

a buffer region surrounding the island region for preventing an electrical interference between the island region and the first element formation region;

a source region and a drain region provided in the island region, a first one of the source region and the drain region being looped around a second one of the source region and the drain region;

a source electrode and a drain electrode respectively provided on the source region and the drain region, a first one of the source electrode and the drain electrode connected to the first one of the source region and the drain region, and extending between the trench region and a second one of the source electrode and the drain electrode; and

a gate electrode provided over a portion of the island region between the source region and the drain region,

wherein when a first voltage having a specific polarity is applied to the first one of the source electrode and the drain electrode, a second voltage having the specific polarity is applied to one of a specific portion of the island region, the trench region, and the support substrate, the specific portion of the island region extending between the trench region and the first one of the source electrode and the drain electrode.

2. The semiconductor apparatus of claim 1, further comprising an auxiliary electrode provided on the specific portion between the trench region and the first one of the source electrode and the drain electrode, for receiving the second voltage.

3. The semiconductor apparatus of claim 2, wherein the auxiliary electrode is electrically connected to the first one of the source electrode and the drain electrode.

4. The semiconductor apparatus of claim 2, wherein the auxiliary electrode extends over the trench region.

5. The semiconductor apparatus of claim 2, wherein:

the trench region is filled with a trench region semiconductor layer at least at a surface portion thereof; and

the auxiliary electrode is electrically connected to the trench region semiconductor layer.

6. The semiconductor apparatus of claim 2, wherein the auxiliary electrode is looped to correspond to a shape of the trench region.

7. The semiconductor apparatus of claim 1, wherein the specific polarity of the first voltage and the second voltage is positive.

8. The semiconductor apparatus of claim 1, wherein the first voltage and the second voltage are a ground level.

9. A semiconductor apparatus comprising:

a semiconductor substrate including a first element formation region and a second element formation region as an island region that is surrounded by a trench region, the trench region electrically isolating the island region from the first element formation region;

a buffer region surrounding the trench region for preventing an electrical interference between the island region and the first element formation region;

a source region and a drain region provided in the island region, a first one of the source region and the drain region being looped to be concentrically provided around a second one of the source region and the drain region;

a source electrode and a drain electrode respectively provided on the source region and the drain region, a first one of the source electrode and the drain electrode connected to the first one of the source region and the drain region, and extending adjacently to the trench region more than a second one of the source electrode and the drain electrode;

a gate electrode provided over a portion of the island region between the source region and the drain region; and

an auxiliary electrode provided between the trench region and the first one of the source electrode and the drain electrode,

wherein when a first voltage having a specific polarity is applied to the first one of the source electrode and the drain electrode, a second voltage having the specific polarity is applied to the auxiliary electrode.

10. The semiconductor apparatus of claim 9, wherein the auxiliary electrode is looped to correspond to a shape of the trench region.

11. The semiconductor apparatus of claim 9, wherein the auxiliary electrode is electrically connected to the first one of the source electrode and the drain electrode.

12. The semiconductor apparatus of claim 9, wherein the first one of the source electrode and the drain electrode are looped to correspond to a shape of the first one of the source region and the drain region.

13. The semiconductor apparatus of claim 9, wherein the auxiliary electrode is disposed over the trench region.

14. The semiconductor apparatus of claim 9, wherein the auxiliary electrode is independent from the first one of the source electrode and the drain electrode.

15. The semiconductor apparatus of claim 9, wherein:

the trench region is filled with a trench region semiconductor layer at least at a surface portion thereof; and

the auxiliary electrode is electrically connected to the trench region semiconductor layer.

16. The semiconductor apparatus of claim 15, wherein the auxiliary electrode is electrically connected to the first one of the source electrode and the drain electrode.

17. The semiconductor apparatus of claim 9, wherein the first and second voltages are positive, and the buffer region is grounded.

18. The semiconductor apparatus of claim 9, wherein:

the semiconductor substrate includes;

a support substrate;

an insulation layer provided on the support substrate; and

a semiconductor layer provided on the insulation layer and having the first element formation region and the second element formation region, and

a third voltage is applied to the support substrate so that a potential difference between the support substrate and the first one of the source region and the drain region is decreased.

19. A semiconductor apparatus comprising:

a support substrate;

an insulation layer provided on the support substrate;

a semiconductor layer provided on the insulation layer and including a first island region and a second island region respectively surrounded by a first trench region and a second trench region to be electrically isolated from one another;

a first semiconductor element provided in the first island region and including;

a first source region and a first drain region provided in the first island region, a first one of the first source region and the first drain region being looped around a second one of the first source region and the first drain region;

a first source electrode and a first drain electrode respectively provided on the first source region and the first drain region; and

a first gate electrode provided over a portion of the first island region between the first source region and the first drain region; and

support substrate connection means electrically connected to the support substrate for applying a voltage to the support substrate so that a potential difference between the support substrate and the first one of the first source region and the first drain region becomes small.

20. The semiconductor apparatus of claim 19, further comprising:

a second semiconductor element provided in the second island region and including;

a second source region and a second drain region provided in the second island region, a first one of the second source region and the second drain region being looped around a second one of the second source region and the second drain region;

a second source electrode and a second drain electrode respectively provided on the second source region and the second drain region; and

a second gate electrode provided over a portion of the second island region between the second source region and the second drain region;

a buffer region surrounding the second island region for preventing an electrical interference between the first semiconductor element provided in the first island region and the second semiconductor element provided in the second island region; and

buffer region connection means electrically connected to the buffer region for applying a voltage to the buffer region so that a potential difference between the buffer region and the first one of the second source region and the second drain region becomes small.

21. The semiconductor apparatus of claim 20, wherein a first one of the first semiconductor element and the second semiconductor element is a P channel MOSFET, and a second one of the first semiconductor element and the second semiconductor element is an N channel MOSFET.