Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density

• US 6,150,708 A
• Filed: 11/13/1998
• Issued: 11/21/2000
• Est. Priority Date: 11/13/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gardner, Mark I., Fulford, H. Jim, May, Charles E.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/191,305
• Time in Patent Office: 739 Days
• Field of Search: 257/446, 257/501, 257/506, 257/777, 257/778, 257/774, 257/708, 257/618
• US Class Current: 257/618
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

An integrated circuit employing both sides of a base substrate or wafer and a method of making the same are provided. In one aspect, the integrated circuit includes a base substrate that has a first side and a second side opposite the first side. The first side has a first semiconductor layer and a first isolation structure positioned thereon wherein the first side surrounds the first semiconductor layer. The second side has a second semiconductor layer and a second isolation structure positioned thereon wherein the second isolation structure surrounds the second semiconductor layer. A first circuit device is positioned on the first semiconductor layer. A second circuit device is positioned on the second semiconductor layer. The method enables simultaneous processing of both sides of a given wafer. Fabrication efficiency is increased through higher throughput and much higher yields per wafer.

Claims

1. A semiconductor wafer, comprising:

a base substrate having a first side and a second side;

a first semiconductor layer positioned on the first side;

a first isolation structure positioned on the first side and around the first semiconductor layer;

a second semiconductor layer positioned on the second side; and

a second isolation structure positioned on the second side and around the second semiconductor layer.

2. The semiconductor wafer of claim 1, wherein the base substrate is composed of silicon and the first and second semiconductor layers are composed of silicon.

3. The semiconductor wafer of claim 2, wherein the first and second semiconductor layers contain a dopant of a first conductivity type.

4. The semiconductor wafer of claim 2, wherein the first semiconductor layer contains a dopant of a first conductivity type and the second semiconductor layer contains a dopant of a second conductivity type.

5. The semiconductor wafer of claim 1, wherein the first and second isolation structures are composed of silicon dioxide, TEOS, silicon oxynitride, or silicon nitride.

6. The semiconductor wafer of claim 1, comprising a first electronic circuit device positioned on the first semiconductor layer and a second electronic circuit device positioned on the second semiconductor layer.

7. The semiconductor wafer of claim 1, comprising a first integrated circuit positioned on the first semiconductor layer and a second integrated circuit positioned on the second semiconductor layer.

8. A semiconductor wafer, comprising:

a semiconductor substrate having a first side with a first plurality of active areas and a second side with a second plurality of active areas;

a firs isolation structure positioned on the first side and laterally isolating the first plurality of active areas; and

a second isolation structure positioned on the second side and laterally isolating the second plurality of active areas.

9. Thc semiconductor wafer of claim 8, wherein the semiconductor substrate is composed of silicon.

10. The semiconductor wafer of claim 8, wherein the first and second isolation structures are composed of silicon dioxide, TEOS, silicon oxynitride, or silicon nitride.

11. The semiconductor water of claim 8, comprising a first electronic circuit device positioned on one of the first plurality of active areas and a second electronic circuit device positioned on one of the second plurality of active areas.

12. The semiconductor wafer of claim 8, comprising a first integrated circuit positioned on one of the first plurality of active areas and a second integrated circuit positioned on one of the second plurality of active areas.

13. An integrated circuit, comprising:

a base substrate having a first side and a second side opposite the first side;

a first semiconductor layer and a first isolation structure positioned on the first side, the first isolation structure surrounding the first semiconductor layer;

a first circuit device positioned on the first semiconductor layer;

a second semiconductor layer and a second isolation structure positioned on the second side, the second isolation structure surrounding the second semiconductor layer; and

a second circuit device positioned on the second semiconductor layer.

14. The integrated circuit of claim 13, wherein the first and second circuit devices comprise transistors.

15. The integrated circuit of claim 14, wherein the first and second transistors comprise field effect transistors.

16. The integrated circuit of claim 14, wherein the first and second semiconductor layer are composed of silicon.

17. The integrated circuit of claim 15, wherein the first and second semiconductor layers contain a dopant of a first conductivity type.

18. The integrated circuit of claim 15, wherein the first semiconductor layer contains a dopant of a first conductivity type and the second semiconductor layer contains a dopant of a second conductivity type.

19. The integrated circuit of claim 13, wherein the first and second isolation structures are composed of silicon dioxide, TEOS, silicon oxynitride, or silicon nitride.

20. An integrated circuit, comprising:

a base substrate having a first side and a second side opposite the first side, the first side having a first semiconductor layer and a first isolation structure positioned thereon wherein the first isolation structure surrounds the first semiconductor layer, the second side having a second semiconductor layer and a second isolation structure positioned thereon wherein the second isolation structure surrounds the second semiconductor layer;

a first circuit device positioned on the first semiconductor layer; and

a second circuit device positioned on the second semiconductor layer.

21. The integrated circuit of claim 20, wherein the first and second circuit devices comprise transistors.

22. The integrated circuit of claim 21, wherein the first and second transistors comprise field effect transistors.

23. The integrated circuit of claim 20, wherein the first and second semiconductor layers are composed of silicon.

24. The integrated circuit of claim 23, wherein the first and second semiconductor layers contain a dopant of a first conductivity type.

25. The integrated circuit of claim 23, wherein the first semiconductor layer contains a dopant of a first conductivity type and the second semiconductor layer contains a dopant of a second conductivity type.

26. The integrated circuit of claim 20, wherein the first and second isolation structures are composed of silicon dioxide, TEOS, silicon oxynitride, or silicon nitride.