Multilevel logic field programmable device

• US 6,150,836 A
• Filed: 06/30/1999
• Issued: 11/21/2000
• Est. Priority Date: 06/13/1997
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Malleable Technologies, Inc. (Microchip Technology Incorporated)
• Inventors: Abbott, Curtis
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/346,556
• Time in Patent Office: 510 Days
• Field of Search: 326/38, 326/39, 326/37, 326/52, 326/59, 712/37, 712/43, 712/42, 712/33, 712/21, 712/227, 712/229
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A method and apparatus for providing a programmable logic datapath that may be used in a field programmable device. According to one aspect of the invention, a programmable logic datapath is provided that includes a plurality of logic elements to perform various (Boolean) logic operations. The programmable logic datapath further includes circuitry to selectively route and select operand bits between the plurality of logic elements (operand bits is used hereinafter to refer to input bits, logic operation result bits, etc., that may be generated within the logic datapath). In one embodiment, by providing control bits concurrently with operand bits to routing and selection (e.g., multiplexing) circuitry, the programmable logic datapath of the invention can provide dynamic programmability to perform a number of logic operations on inputs of various lengths on a cycle-by-cycle basis.

Claims

1. A field programmable logic device comprising:

a plurality of sources each providing an output;

a selector unit to separately select for each part of its output the corresponding part of the output from one of said plurality of sources; and

a programmable logic datapath coupled to said selector unit including,

a rearrangement circuit coupled to receive said output of said selector unit;

a selective field negation circuit coupled to said rearrangement circuit; and

a plurality of reduction networks each coupled to receive the outputs of said selective field negation circuit and each including a series of logic levels coupled together to selectively reduce those outputs using XOR, OR, and selective negation circuitry down to one bit.

2. The field programmable logic device of claim 1, wherein said rearrangement circuit at least one of selects and re-orders the bits of said output of said selector unit.

3. The field programmable logic device of claim 1 wherein each of said plurality of reduction networks also includes a subset selection circuit to selectively pass the outputs of said selective field negation circuit to the first in the series of logic levels.

4. The field programmable logic device of claim 1 further comprising:

a decoder; and

a memory coupled to said programmable logic datapath and said selector unit and addressable by said decoder, said memory for storing or having stored therein a plurality of sets of control signals, each set of control signals when applied to said programmable logic datapath causing said programmable logic datapath to perform a different function.

5. The field programmable logic device of claim 1 wherein said plurality of sources includes an input array and a register bank.

6. The field programmable logic device of claim 1, wherein each of said plurality of reduction networks also includes:

a transposition circuit to selectively interchange with another of said plurality of reduction networks data being routed from one of said logic levels to the next.

7. The field programmable logic device of claim 1, wherein the parts selected by said selector unit are bytes.

8. The field programmable logic device of claim 7 wherein each of said plurality of reduction networks also includes a subset selection circuit to selectively pass the outputs of said selective field negation circuit to the first in the series of logic levels.

9. An apparatus comprising:

a programmable logic datapath having a plurality of inputs, said programmable logic datapath including a plurality of reduction networks, each of said plurality of reduction networks including,

at least three logic levels coupled in series, wherein two dynamic reduction paths are provided through said logic levels that each reduce data provided at the plurality of inputs to one bit, each of the logic levels logically combines one or more mutually exclusive groups of data on one of the dynamic reduction paths by XOR operations, each of the logic levels logically combines corresponding groups of data on the other of the dynamic reduction paths by OR operations, each of the logic levels separately selectively switches the XOR and OR outputs in each corresponding group, each logic level also separately selectively negates the output in each corresponding group along one of the dynamic reduction paths.

10. The apparatus of claim 9 wherein said programmable logic datapath further comprises:

a rearrangement circuit coupled to the plurality of inputs; and

a selective field negation circuit coupled to said rearrangement circuit and each of said plurality of reduction networks.

11. The apparatus of claim 9, wherein said programmable logic datapath further comprises a rearrangement circuit to selectively couple data provided at the plurality of inputs to different ones of a plurality of rearrangement circuit outputs, said plurality of reduction networks coupled to said rearrangement circuit outputs.

12. The apparatus of claim 11, wherein said programmable logic datapath further comprises a negation circuit coupled between the rearrangement circuit and the plurality of reduction networks to conditionally complement data provided at different ones of the plurality of rearrangement circuit outputs.

13. The apparatus of claim 9 wherein each of said plurality of reduction networks also includes a subset selection circuit coupled to selectively pass the provided data to both of the dynamic reduction paths.

14. The apparatus of claim 9 further comprising:

a decoder; and

a memory coupled to said programmable logic datapath and addressable by said decoder, said memory for storing or having stored therein a plurality of sets of control signals, each set of control signals when applied to said programmable logic datapath causing said programmable logic datapath to perform a different function.

15. The apparatus of claim 9, wherein each of said plurality of reduction networks also includes:

a transposition circuit to selectively interchange with another reduction network data being routed from one of said logic levels to the next according to the dynamic reduction paths.

16. The apparatus of claim 9, further comprising:

a plurality of sources each providing an output; and

a selector unit coupled to said plurality of sources and said plurality of inputs to said programmable logic datapath, said selector unit to separately select for each part of its output the corresponding part of the output from one of the plurality of sources.

17. The apparatus of claim 16 wherein said plurality of sources includes an input array and a register bank.

18. The apparatus of claim 16, wherein the parts selected by said selector unit are bytes.

19. A programmable logic datapath comprising:

a plurality of inputs; and

a plurality of reduction networks, each of said plurality of reduction networks including,

a first and second level one logic circuits each coupled to receive a first and second copy of data provided at a different set of said plurality of inputs, each level one logic circuit respectively performing an XOR and OR logic operation on said first and second copy to respectively provide a first and second logic output;

an alignment and negation circuit, coupled to said first and second outputs of said first and second level one logic circuits, to selectively provide different combinations of one output from each of said first and second level one logic circuits at each of a first and second alignment output, as well as selectively negate at least one of the values provided on one of the first and second alignment outputs; and

a level two logic circuit having a first and second input respectively coupled to said first and second outputs of said alignment and negation circuit, said level two logic circuit respectively performing an XOR and OR operation on data received at said first and second inputs.

20. The programmable logic datapath of claim 19 further comprising:

a plurality of level one logic circuits and corresponding alignment and negation circuits; and

a plurality of level two logic circuits coupled in similar manner to pairs of said plurality of level one logic circuits.

21. The programmable logic datapath of claim 20 further comprising:

a plurality of alignment and negation circuits coupled to said level two logic circuit and said plurality of level two logic circuits according to mutually exclusive pairs; and

one or more additional levels of logic circuits and corresponding alignment and negation circuits coupled in similar series to said plurality of alignment and negation circuits coupled to said level two logic circuit and said plurality of level two logic circuits.

22. The programmable logic datapath of claim 21 further comprising:

a final level of logic circuit and corresponding negation circuit coupled in similar manner to provide one bit representing the reduction of the data provided at the plurality of inputs.

23. The programmable logic datapath of claim 21 further comprising:

a transposition circuit to selectively interchange data being routed between one level of logic circuits and corresponding alignment and negation circuits and an adjacent level of logic circuits in different ones of said plurality of reduction networks.

24. The programmable logic datapath of claim 19, wherein at least one of said plurality of reduction networks further includes:

a subset selection circuit coupled to said plurality of inputs to selectively pass data provided at different inputs of each of said sets of inputs respectively to said first and second level one logic circuits.

25. The programmable logic datapath of claim 19 further comprising:

a rearrangement circuit coupled to said plurality of inputs; and

a selective field negation circuit coupled to said rearrangement circuit and each of said plurality of reduction networks.

26. An apparatus comprising:

a plurality of sources each providing an output;

a selector unit to separately select for each part of its output the corresponding part of the output from one of said plurality of sources; and

a programmable logic datapath coupled to said selector unit including,

a plurality of reduction networks each including,

at least three logic levels coupled together in series including,

a first logic level to group its inputs into mutually exclusive groups, separately perform a first and second logic operations on separate copies of the inputs within each group, and optionally switch the combined results within each group before provision to the next logic level, and

each of the remaining logic levels to combine the groups provided to it from the previous logic level into mutually exclusive super groups, perform the first and second logic operations respectively on the first and second optionally switched combined results of the groups, and optionally switch the inputs in each of the groups before provision to the next logic level.

27. The apparatus of claim 26 wherein said programmable logic datapath further comprises:

a rearrangement circuit coupled to receive the output from said selector unit; and

a selective field negation circuit coupled to said rearrangement circuit and each of said plurality of reduction networks.

28. The apparatus of claim 26, wherein said programmable logic datapath further comprises a rearrangement circuit to selectively couple the output of said selector unit to different ones of a plurality of rearrangement circuit outputs, said first logic level in each of said plurality of reduction networks coupled to said plurality of rearrangement circuit outputs.

29. The apparatus of claim 28, wherein said programmable logic datapath further comprises a negation circuit coupled between the rearrangement circuit and the plurality of reduction networks to separately selectively complement data on different ones of the plurality of rearrangement circuit outputs.

30. The apparatus of claim 26 wherein each of said plurality of reduction networks also includes a subset selection circuit coupled provide the inputs to said first logic level.

31. The apparatus of claim 26 further comprising:

a decoder; and

a memory coupled to said programmable logic datapath and said selector unit and addressable by said decoder, said memory for storing or having stored therein a plurality of sets of control signals, each set of control signals when applied to said programmable logic datapath causing said programmable logic datapath to perform a different function.

32. The apparatus of claim 26 wherein said plurality of sources includes an input array and a register bank.

33. The apparatus of claim 26, wherein each of said plurality of reduction networks also includes:

a transposition circuit to selectively interchange with another reduction network data being routed from one of said logic levels to the next.

34. The apparatus of claim 26, wherein the first and second logic operations of at least one logic level in each of said plurality of reduction networks are XOR and OR operations along with selective negation according to DeMorgan'"'"'s Law.

35. The apparatus of claim 26, wherein the parts selected by said selector unit are bytes.

36. A machine-implemented method comprising:

receiving an output from each of a plurality of sources;

separately selecting for each part of a current output a corresponding part of the output from one of said plurality of sources, wherein the bits of said current output form a plurality of mutually exclusive groups; and

performing the following in each of a plurality of reduction networks,

duplicating said current output to form a first and second version of each group,

reducing the first and second version of each group through logic operations to provide for each group a first and second output that are selectively switched and one of which is optionally negated, where the groups form mutually exclusive sets,

reducing the first and second output of each group within each set through logic operations to provide for each set a first and second output that are selectively switched and one of which is optionally negated, where the sets form mutually exclusive supersets, and

reducing the first and second output of each set within each superset through logic operations to provide for each superset a first and second output that are selectively switched and one of which is optionally negated.

37. The machine-implemented method of claim 36, wherein each of said plurality of reduction networks also performs the following:

selectively removing different sets of bits in the current output before said duplicating.

38. The machine-implemented method of claim 36, wherein each of said plurality of reduction networks also perform the following:

continuing reducing in like manner until the current output and the duplicate have each been reduced to a single bit.

39. The machine-implemented method of claim 38, wherein said continuing reducing includes interchanging between different ones said plurality of reduction networks data generated by one of said reducings and the next reducing.

40. The machine-implemented method of claim 38 further comprising:

for each of the plurality of reduction networks, selecting between the single bits to provide a bit in a collective output of the plurality of reduction networks.

41. The machine-implemented method of claim 36 further comprising:

rearranging different bits in the current output before said performing.

42. The machine-implemented method of claim 41, wherein said rearranging includes replacing certain bits of said current output with a duplicate of other bits of said current output.

43. The machine-implemented method of claim 36 further comprising:

negating different bits of said current output before said performing.

44. A machine-implemented method comprising:

receiving a plurality of inputs, wherein said plurality of inputs form a plurality of mutually exclusive groups;

duplicating said plurality of inputs to form a first and second version of each group;

reducing the first and second version of each group to provide a first and second output for each group by performing the following for each group,

logically combining the inputs within the first version of that group with an XOR operation;

logically combining the inputs within the second version of that group with an OR operation;

selectively switching the result of the logic operation on the first and second version in that group between the first and second outputs for that group; and

reducing the first and second output of each group to provide a first and second output for each set, where the groups form mutually exclusive sets, by performing the following for each set,

logically combining the first output for the groups within that set with an XOR operation;

logically combining the second output for the groups within that set with an OR operation;

selectively switching the result of the logic operation on the first and second output for that set between the first and second outputs for that set.

45. The machine-implemented method of claim 44, wherein said receiving said plurality of inputs further comprises:

selectively blocking different sets of the plurality of inputs.

46. The machine-implemented method of claim 44, wherein said selectively switching includes selectively negating at least on of the first and second outputs.

47. The machine-implemented method of claim 44 further comprising:

continuing reducing in like manner until the plurality of inputs and the duplicate of the plurality of inputs have each been reduced to a single bit.

48. The machine-implemented method of claim 47, wherein said method is separately performed on two separately controlled reduction networks, and wherein said continuing reducing includes interchanging between different ones of said plurality of reduction networks data generated by one of said reducings and the next.

49. The machine-implemented method of claim 44, wherein said receiving further comprises:

rearranging different ones of said plurality of inputs.

50. The machine-implemented method of claim 44, wherein said rearranging includes replacing certain ones of said plurality of inputs with a duplicate of other ones of said plurality of inputs.

51. The machine-implemented method of claim 44, wherein said receiving said plurality of inputs further comprises:

negating different ones of said plurality of inputs.