FPGA configurable logic block with multi-purpose logic/memory circuit

• US 6,150,838 A
• Filed: 02/25/1999
• Issued: 11/21/2000
• Est. Priority Date: 02/25/1999
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wittig, Ralph D., Mohan, Sundararajarao, Carberry, Richard A.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tran, Anh Q.
• Application Number:
  US09/258,024
• Time in Patent Office: 635 Days
• Field of Search: 326/38, 326/39, 326/41
• US Class Current: 326/39
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of programmable elements is programmable both from configuration lines during a configuration mode, and by data transmitted on the interconnect resources through the multiplexer/demultiplexer circuit. In one embodiment, the programmable elements of the array are connected in pairs to product term generation circuitry. Product terms generated by the product term circuitry are passed to a macrocell circuit to perform programmable array logic (PAL) logic operations. In another embodiment, a CLB includes four LMCs and a multiplier circuit such that large amounts of logic are locally implemented, thereby avoiding signal delays associated with transmission over general purpose interconnect resources within a PLD.

Claims

1. A programmable logic device including a plurality of configurable logic blocks and interconnect resources for transmitting signals to the configurable logic blocks, each configurable logic block including a logic/memory circuit comprising:

a first plurality of input terminals for receiving a first set of input signals from the interconnect resources;

a decoder for generating address signals in response to the first plurality of input signals;

an array including programmable elements for storing a plurality of bit values, word lines connected to the decoder for receiving the address signals, and bit lines for transmitting bit values to the programmable elements in response to the address signals;

an input control circuit connected to the first plurality of input terminals for selectively transmitting the first set of input signals onto a group of the bit lines; and

a product term circuit for generating a plurality of product terms in response to the first set of input signals transmitted on the group of the bit lines and the bit values stored in the programmable elements.

2. The programmable logic device according to claim 1,

wherein the input control circuit includes a first pass transistor connected between a first input terminal and a first bit line, an inverter having an inverter input terminal connected to the first input terminal, and a second pass transistor connected between an output terminal of the inverter and a second bit line;

and

wherein the first and second pass transistors are controlled by a control signal to turn on such that an input signal is passed to the first and second bit lines during a first operating mode, and to turn off such that the input signal is isolated from the first and second bit lines during a second operating mode.

3. The programmable logic device according to claim 1, wherein the logic/memory circuit further comprises:

a second group plurality of input terminals for receiving a second set of input signals;

a data input terminal for receiving a write bit value from the interconnect resources; and

a multiplexing/demultiplexing circuit connected to the bit lines, wherein the multiplexing/demultiplexing circuit is selectively controllable to pass a selected bit value read from the programmable elements in response to the second set of input signals in a first mode, and controllable to pass the write bit value from the data input terminal to a selected bit line in response to the second set of input signals in a second mode.

4. The programmable logic device according to claim 1, wherein the logic/memory circuit further comprises a macrocell circuit for generating a sum-of-products value in response to the plurality of product terms.

5. The programmable logic device according to claim 1, wherein the decoder comprises:

a first input terminal for receiving a first input signal;

a second input terminal for receiving a second input signal;

a write control terminal for receiving a write control signal;

a first logic gate for generating a first write address signal in response to the first and second input signals and the write control signal; and

a second logic gate for generating a first read address signal in response to the first and second input signals.

6. The programmable logic device according to claim 5, wherein the decoder further comprises:

a fourth input terminal for receiving a configuration control signal; and

a write control circuit for passing the first write address signal to the array in response to the configuration control signal.

7. The programmable logic device according to claim 5,

wherein the programmable elements of the array are arranged in rows and columns, each row of programmable elements being connected to an associated write bit line and an associated read bit line, each column of programmable elements being connected to an associated write word line and an associated read word line;

wherein the first write address signal generated by the first logic gate is transmitted onto a first write word line; and

wherein the first read address signal generated by the second logic gate is transmitted onto a first read word line.

8. The programmable logic device according to claim 7, wherein each programmable element of the array comprises:

a latch for storing a bit value;

a write transistor having a first terminal connected to the write bit line, a second terminal connected to the latch, and a gate connected to the write word line;

an inverter having an input terminal connected to the latch and an output terminal; and

a read transistor having a first terminal connected to the read bit line, a second terminal connected to the output terminal of the inverter, and a gate connected to the read word line.

9. The programmable logic device according to claim 7, further comprising:

a read/write control circuit having a first pass transistor connected to a first write bit line, a second pass transistor connected to a first read bit line, and an output terminal connected to the first and second pass transistors; and

a multiplexing/demultiplexing circuit connected to the output terminal of the read/write control circuit, the multiplexing/demultiplexing circuit having an output terminal and a data input terminal,

wherein the read/write control circuit and the multiplexing/demultiplexing circuit are selectively controllable to pass a bit value from the first read bit line to the output terminal of the multiplexing/demultiplexing circuit in a first mode, and controllable to pass a write bit value from the data input terminal to the first write bit line in a second mode.

10. The programmable logic device according to claim 9, wherein the logic/memory circuit further comprises a macrocell circuit for generating a sum-of-products value in response to the plurality of product terms, and wherein the multiplexing/demultiplexing circuit comprises:

a multiplexer circuit for selectively passing the bit value from the first read bit line; and

an output control circuit for transmitting either the bit value or the sum-of-products value from the macrocell circuit to the output terminal of the multiplexing/demultiplexing circuit.

11. The programmable logic device according to claim 10,

wherein the multiplexing/demultiplexing circuit further comprises:

a first plurality of two-input multiplexers including a first multiplexer having a first input terminal selectively connected to the first write bit line and the first read bit line, and a second input terminal selectively connected to a second write bit line and a second read bit line,

a second plurality of two-input multiplexers including a second multiplexer having an input terminal connected to an output terminal of the first multiplexer and further including a third multiplexer,

a third plurality of two-input multiplexers including a fourth multiplexer having a first input terminal connected to an output terminal of the second multiplexer, and a second input terminal connected to an output terminal of the third multiplexer, and

a fifth multiplexer having an input terminal connected to an output terminal of the third multiplexer; and

wherein the output control circuit comprises a sixth two-input multiplexer for selectively passing a first bit value from one of the second multiplexer and the fourth multiplexer to a first output terminal, and further comprises a seventh two-input multiplexer for selectively passing a second bit value from one of the third multiplexer and the fifth multiplexer to a second output terminal.

12. The programmable logic device according to claim 1,

wherein the input control circuit comprises a first transistor for selectively applying a first input signal onto a first bit line and a second transistor for applying an inverted form of the first input signal onto a second bit line;

wherein the array comprises;

a first programmable element having a latch for storing a first bit value,

a first pass transistor having a first terminal connected to the first bit line, a second terminal connected to a node, and a gate connected to the latch of the first programmable element,

a second pass transistor having a first terminal connected to the second bit line, a second terminal connected to the node, and a gate connected to the latch of the first programmable element, and

a second programmable element having a latch for storing a second bit value; and

wherein the product term circuit comprises;

a cell logic circuit having a first input terminal connected to the node and a second input terminal connected to the latch of the second programmable element, and

an AND circuit for generating a product term in response to an output signal generated by the cell logic circuit.

13. The programmable logic device according to claim 1, wherein the decoder comprises:

a first input terminal for receiving a first input signal;

a second input terminal for receiving a second input signal;

a write control terminal for receiving a write control signal; and

a logic gate for generating an address signal in response to the first and second input signals and the write control signal.

14. The programmable logic device according to claim 13, wherein the decoder further comprises:

a fourth input terminal for receiving a configuration control signal; and

a write control circuit for passing the address signal to the array in response to the configuration control signal.

15. The programmable logic device according to claim 13,

wherein the programmable elements of the array are arranged in rows and columns, each row of programmable elements being connected to an associated bit line, and each column of programmable elements being connected to an associated word line, and

wherein the address signal generated by the logic gate is transmitted onto a first word line.

16. The programmable logic device according to claim 15, wherein each programmable element of the array comprises:

a latch for storing a bit value; and

a write transistor having a first terminal connected to the bit line, a second terminal connected to the latch, and a gate connected to the word line.

17. The programmable logic device according to claim 15, further comprising a multiplexing/demultiplexing circuit having an output terminal and a data input terminal, the multiplexing/demultiplexing circuit being connected to a first bit line and being selectively controllable to pass a bit value from the first bit line to the interconnect resources in a first mode, and controllable to pass a write bit value from the data input terminal to the first bit line in a second mode.

18. The programmable logic device according to claim 17, wherein the logic/memory circuit further comprises a macrocell circuit for generating a sum-of-products value in response to the plurality of product terms, and wherein the multiplexing/demultiplexing circuit comprises:

a multiplexer circuit for selectively passing the bit value from the first bit line; and

an output control circuit for transmitting either the bit value or the sum-of-products value from the macrocell circuit to the output terminal of the multiplexing/demultiplexing circuit.

19. The programmable logic device according to claim 18,

wherein the multiplexing/demultiplexing circuit further comprises:

a first plurality of two-input multiplexers including a first multiplexer having a first input terminal connected to the first bit line, and a second input terminal connected to a second bit line,

a second plurality of two-input multiplexers including a second multiplexer having an input terminal connected to an output terminal of the first multiplexer and further including a third multiplexer,

a third plurality of two-input multiplexers including a fourth multiplexer having a first input terminal connected to an output terminal of the second multiplexer, and a second input terminal connected to an output terminal of the third multiplexer, and

a fifth multiplexer having an input terminal connected to an output terminal of the third multiplexer; and

wherein the output control circuit comprises a sixth two-input multiplexer for selectively passing a first bit value from one of the second multiplexer and the fourth multiplexer to a first output terminal, and further comprises a seventh two-input multiplexer for selectively passing a second bit value from one of the third multiplexer and the fifth multiplexer to a second output terminal.

20. The programmable logic device according to claim 1,

wherein the decoder generates a first write address signal in response to a first input signal, a second input signal, and a write control signal, and

wherein the array further comprises a hard-wired decode circuit for generating a first read address signal and a second read address signal in response to the first input signal and the second input signal.

21. The programmable logic device according to claim 20, wherein the decoder further comprises:

a first line for transmitting the first input signal;

a first inverter for inverting the first input signal;

a second line connected to the first inverter for transmitting the inverted first input signal;

a third line for transmitting the second input terminal;

a second inverter for inverting the second input signal;

a fourth line connected to the second inverter for transmitting the inverted second input signal;

a write control terminal for receiving the write control signal; and

a first logic gate for generating a first write address signal in response to the first and second input signals and the write control signal.

22. The programmable logic device according to claim 21, wherein the decoder further comprises:

a fourth input terminal for receiving a configuration control signal; and

a write control circuit for passing the first write address signal to the array in response to the configuration control signal.

23. The programmable logic device according to claim 21, wherein the hard-wired decode circuit further comprises:

a first read word line connected to one of the first, second, third, and fourth lines for transmitting the first read address signal; and

a second read word line connected to another of the first, second, third, and fourth lines for transmitting the second read address signal.

24. The programmable logic device according to claim 20,

wherein the programmable elements of the array are arranged in rows and columns, each row of programmable elements being connected to an associated write bit line and an associated read bit line, each column of programmable elements being connected to an associated write word line and an associated pair of read word lines;

wherein the first write address signal is transmitted onto a first write word line;

wherein the first read address signal is transmitted onto a first read word line; and

wherein the second read address signal is transmitted onto a second read word line.

25. The programmable logic device according to claim 24, wherein each programmable element of the array comprises:

a latch for storing a bit value;

a write transistor having a first terminal connected to the write bit line, a second terminal connected to the latch, and a gate connected to the write word line;

an inverter having an input terminal connected to the latch and further having an output terminal;

a first read transistor having a first terminal connected to the output terminal of the inverter, a second terminal, and a gate connected to the first read word line; and

a second read transistor having a first terminal connected to the second terminal of the first read transistor, a second terminal connected to the read bit line, and a gate connected to the second read word line.

26. The programmable logic device according to claim 24, further comprising:

a read/write control circuit having a first pass transistor connected to a first write bit line, a second pass transistor connected to a first read bit line, and an output terminal connected to the first and second pass transistors; and

a multiplexing/demultiplexing circuit connected to the output terminal of the read/write control circuit, the multiplexing/demultiplexing circuit having an output terminal and a data input terminal,

wherein the read/write control circuit and the multiplexing/demultiplexing circuit are selectively controllable to pass a bit value from the first read bit line to the output terminal of the multiplexing/demultiplexing circuit in a first mode, and controllable to pass a write bit value from the data input terminal to the first write bit line in a second mode.

27. The programmable logic device according to claim 26, wherein the logic/memory circuit further comprises a macrocell circuit for generating a sum-of-products value in response to the plurality of product terms, and wherein the multiplexing/demultiplexing circuit comprises:

a multiplexer circuit for selectively passing the bit value from the first read bit line; and

an output control circuit for transmitting either the bit value or the sum-of-products value from the macrocell circuit to the output terminal of the multiplexing/demultiplexing circuit.

28. The programmable logic device according to claim 27,

wherein the multiplexing/demultiplexing circuit further comprises:

a first plurality of two-input multiplexers including a first multiplexer having a first input terminal selectively connected to the first write bit line and the first read bit line, and a second input terminal selectively connected to a second write bit line and a second read bit line,

a second plurality of two-input multiplexers including a second multiplexer having an input terminal connected to an output terminal of the first multiplexer and further including a third multiplexer,

a third plurality of two-input multiplexers including a fourth multiplexer having a first input terminal connected to an output terminal of the second multiplexer, and a second input terminal connected to an output terminal of the third multiplexer, and

a fifth multiplexer having an input terminal connected to an output terminal of the third multiplexer; and

wherein the output control circuit comprises a sixth two-input multiplexer for selectively passing a first bit value from one of the second multiplexer and the fourth multiplexer to a first output terminal, and further comprises a seventh two-input multiplexer for selectively passing a second bit value from one of the third multiplexer and the fifth multiplexer to a second output terminal.

29. A programmable logic device including a plurality of configurable logic blocks and interconnect resources for transmitting signals to the configurable logic blocks, each configurable logic block comprising:

a plurality of input terminals connected to the interconnect resources;

a first switch circuit for transmitting selected input signals from the plurality of input terminals onto a plurality of input lines;

a plurality of logic/memory circuits, each logic/memory circuit comprising;

a plurality of input terminals connected to a group of the plurality of input lines for receiving the selected input signals;

a decoder for generating address signals in response to the selected input signals;

an array including programmable elements for storing a plurality of bit values, word lines connected to the decoder for receiving the address signals, and bit lines for transmitting bit values to the programmable elements in response to the address signals;

an input control circuit connected to the input terminals for selectively transmitting the selected input signals onto the bit lines; and

a product term circuit connected to the bit lines and to the programmable elements for generating a plurality of product terms in response to the selected input signals transmitted on the bit lines and the bit values stored in the programmable elements.

30. The programmable logic device according to claim 29, wherein each logic/memory circuit further comprises:

a macrocell circuit for generating a sum-of-products value in response to the plurality of product terms;

a data input terminal for receiving a write bit value from the interconnect resources; and

a multiplexing/demultiplexing circuit connected to the bit lines and to the macrocell circuit, wherein the multiplexing/demultiplexing circuit is selectively controllable to pass a selected bit value read from a selected bit line to a logic/memory circuit output terminal in a first mode, is controllable to pass the write bit value from the data input terminal to a selected bit line in a second mode, and is controllable to pass the sum-of-products value from the macrocell circuit to the logic/memory circuit output terminal in a third mode.

31. The programmable logic device according to claim 30, wherein each configurable logic block further comprises:

a second switch circuit connected to the logic/memory circuit output terminals and for passing selected bit values from a selected subset of the logic/memory circuit output terminals to a plurality of configurable logic block output terminals;

a register circuit for selectively registering the selected bit values; and

a feedback line bus for transmitting the selected bit values to the first switch circuit.

32. The programmable logic device according to claim 30, wherein the first switch circuit comprises a plurality of multiplexer circuits connected to the plurality of input terminals, each multiplexer circuit comprising:

a first plurality of pass transistors, each pass transistor selectively passing one bit value from one input terminal to a first plurality of common nodes;

a second plurality of pass transistors, each pass transistor selectively passing one bit value from one feedback line of the feedback line bus to a second plurality of common nodes; and

a third plurality of pass transistors for passing one signal from one of the first plurality of common nodes and the second plurality of common nodes to one of the plurality of input lines.

33. The programmable logic device according to claim 31, wherein each configurable logic block further comprises a special purpose logic circuit connected to receive input signals from the first switch circuit, and connected to transmit output signals to the second switch circuit.

34. The programmable logic device according to claim 33, wherein the special purpose logic circuit is a multiplier circuit.

35. The programmable logic device according to claim 30, wherein each configurable logic block further comprises a programmable array logic circuit.

36. The programmable logic device according to claim 30, wherein each configurable logic block further comprises:

a plurality of configurable logic block output terminals connected to the logic/memory circuit output terminals for passing bit values from the logic/memory circuit output terminals to the interconnect resources;

a feedback line bus for transmitting a first selected subset of the bit values from the configurable logic block output terminals to the first switch circuit; and

a register circuit for selectively registering a second selected subset of the bit values transmitted on the configurable logic block output terminals.

37. The programmable logic device according to claim 36, wherein the first switch circuit comprises a plurality of multiplexer circuits connected to the plurality of input terminals, each multiplexer circuit comprising:

a first plurality of pass transistors, each pass transistor selectively passing one bit value from one input terminal to a first plurality of common nodes;

a second plurality of pass transistors, each pass transistor selectively passing one bit value from one feedback line of the feedback line bus to a second plurality of common nodes; and

a third plurality of pass transistors for passing one signal from one of the first plurality of common nodes and the second plurality of common nodes to one of the plurality of input lines.