System for phase-locking a clock to a digital audio signal embedded in a digital video signal

• US 6,151,076 A
• Filed: 02/10/1998
• Issued: 11/21/2000
• Est. Priority Date: 02/10/1998
• Status: Expired due to Term

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Hoffman, Gilbert A., Zink, Scott
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): Sajous, Wesner
• Application Number:
  US09/021,699
• Time in Patent Office: 1,015 Days
• Field of Search: 348/512, 348/513, 348/515, 348/423, 348/462, 348/536, 348/540, 348/544, 360/51, 360/64, 360/30, 331/17, 331/40, 331/41, 331/44, 331/175, 375/2, 375/376, 375/362
• US Class Current: 348/512
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/8106 involving special audio data, e.g. different tracks for different languages
• CPC Class Codes: H04N 5/602 for digital sound signals

Abstract

A system for phase-locking a clock to a digital audio signal embedded within a digital video signal uses an audio extractor, frequency dividers, and an adjusted bandwidth loop filter to prevent phase jitter associated with the digital audio signal preventing the functionality of the phase-lock loop or having unacceptable effects on the generated audio sample frequency signal. Extracted audio samples are divided down and input to a phase detector. The signal is then filtered using a series of loop filters, one of which has an adjusted bandwidth to reject phase jitter. A clock then outputs the generated synthesized audio sample frequency using the output from the series of loop filters, and the synthesized frequency signal is looped back through a second frequency divider to the phase detector.

Claims

1. A method for phase-locking a clock to a digital audio signal embedded within a digital video signal comprising the steps of:

generating a first reference frequency signal from digital audio signal samples embedded within the digital video signal by dividing the frequency of the digital audio signal samples by a divisor such that the period of the first reference frequency is greater or equal to that of phase jitter present in the digital audio signal samples;

generating a second reference frequency signal from an output audio sample frequency signal, the frequency of the output audio sample frequency signal being equal to the frequency of the digital audio signal samples so that, when divided by the divisor, the frequency of the second reference frequency signal equals that of the first reference frequency signal;

generating from the first and second reference frequency signals a low jitter clock control signal, the low jitter clock control signal been result of rejecting the phase jitter present in the digital audio signal samples; and

generating the output audio sample frequency signal from the low jitter clock control signal.

2. The method according to claim 1, wherein the low jitter clock control signal generating step comprises the steps of:

inputting the first and second reference frequency signals into a phase detector; and

filtering output from the phase detector such that the phase jitter present in the digital audio signal samples is rejected and the low jitter clock control signal is produced.

3. The method according to claim 2, wherein the filtering step comprises the step of inputting output from the phase detector through a series of two loop filters, one of which is an adjusted bandwidth loop filter, such loop filter'"'"'s bandwidth configured to a degree which is sufficient to attenuate the phase jitter that is present in the digital audio signal samples, such that the low jitter clock control signal is produced.

4. The method according to claim 2, wherein the filtering step comprises the step of inputting output from the phase detector to a loop filter, such loop filter allowing for a system gain to decline to less than 1 with a phase shift not supporting oscillations at a gain of 1, and such loop filter'"'"'s bandwidth is configured to a degree which is sufficient to attenuate the phase jitter that is present in the digital audio signal samples, such that the low jitter clock control signal is produced.

5. The method according to claim 1, wherein the output audio sample frequency signal generating step comprises the steps of:

inputting the low jitter clock control signal to a VCO;

dividing down an initial output of the VCO to the frequency of the digital audio signal samples; and

outputting the divided down signal as the output audio sample frequency signal.

6. An apparatus for phase-locking a clock to a digital audio signal embedded within a digital video signal comprising:

means for generating a first reference frequency signal from digital audio signal samples embedded within the digital video signal by dividing the frequency of the digital audio signal samples by a divisor such that the period of the first reference frequency is greater or equal to that of phase jitter present in the digital audio signal samples;

means for generating a second reference frequency signal from an output audio sample frequency signal, the frequency of the output audio sample frequency signal being equal to the frequency of the digital audio signal samples so that, when divided by the divisor, the frequency of the second reference frequency signal equals that of the first reference frequency signal;

means for generating from the first and second reference frequency signals a low jitter clock control signal, the low jitter clock control signal been result of rejecting the phase jitter present in the digital audio signal samples; and

means for generating the output audio sample frequency signal from the low jitter clock control signal.

7. The apparatus of claim 6, wherein the low jitter clock control signal generating means comprises:

means for inputting the first and second reference frequency signals into a phase detector; and

means for filtering output from the phase detector such that the phase jitter present in the digital audio signal samples is rejected and the low jitter clock control signal is produced.

8. The apparatus of claim 7, wherein the filtering means comprises means for inputting output from the phase detector through a series of two loop filters, one of which is an adjusted bandwidth loop filter, such loop filter'"'"'s bandwidth configured to a degree which is sufficient to attenuate the phase jitter that is present in the digital audio signal samples, such that the low jitter clock control signal is produced.

9. The apparatus of claim 7, wherein the filtering means comprise means for inputting output from the phase detector to a loop filter, such loop filter allowing for a system gain to decline to less than 1 with a phase shift not supporting oscillations at a gain of 1, and such loop filter'"'"'s bandwidth is configured to a degree which is sufficient to attenuate the phase jitter that is present in the digital audio signal samples, such that the low jitter clock control signal is produced.

10. The apparatus of claim 6, wherein the output audio sample frequency signal generating means comprises:

means for inputting the low jitter clock control signal to a VCO; and

means for dividing down an initial output of the VCO to the frequency of the digital audio signal samples; and

means for outputting the divided down signal as the output audio sample frequency signal.

11. A system for phase-locking a clock to a digital audio signal embedded within a digital video signal comprising:

an audio extractor, operative for extracting digital audio signal samples from the digital video signal;

a first frequency divider coupled to receive the digital audio signal samples from the audio extractor, operative for dividing down the frequency of the digital audio signal samples, having a divisor such that the divided down signal has a period greater or equal to that of phase jitter present in the digital audio signal samples;

a phase detector coupled to receive the divided down signal from the first frequency divider;

a loop filtering apparatus coupled to receive output from the phase detector, such that the phase jitter present in the digital audio signal samples is rejected and a low jitter clock control signal is produced;

a VCO coupled to receive the low jitter clock control signal from the loop filter apparatus; and

a second frequency divider with input coupled to output from the VCO and output coupled for input to the phase detector, such frequency divider having a divisor equal to that of the first frequency divider.

12. The system according to claim 11, wherein the loop filtering apparatus comprises:

a first loop filter coupled to receive output from the phase detector; and

a second loop filter coupled to receive output from the first loop filter, one of which is an adjusted bandwidth loop filter, such loop filter'"'"'s bandwidth configured to a degree which is sufficient to attenuate the phase jitter that is present in the digital audio signal samples, such that the low jitter clock control signal is produced.

13. The system according to claim 11, wherein the loop filtering apparatus comprises a loop filter coupled to receive output from the phase detector, such loop filter allowing for a system gain to decline to less than 1 with a phase shift not supporting oscillations at a gain of 1, and the loop filter'"'"'s bandwidth is configured to a degree which is sufficient to attenuate the phase jitter that is present in the digital audio signal samples, such that the low jitter clock control signal is produced.

14. The system according to claim 11, wherein the VCO comprises:

means for generating a clock signal from the low jitter clock control signal; and

a frequency divider coupled to receive output from the clock signal generating means, such frequency divider having a divisor that divides the clock signal down to the frequency of the digital audio signal samples.