Data packet with embedded mask

• US 6,151,239 A
• Filed: 11/15/1999
• Issued: 11/21/2000
• Est. Priority Date: 10/02/1998
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Batra, Pradeep
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/440,206
• Time in Patent Office: 372 Days
• Field of Search: 365/120, 365/52, 365/63
• US Class Current: 365/120
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence

Abstract

An apparatus and method for storing data in a memory. Mask information is embedded in a data packet and used to indicate memory locations at which data values in the data packet are to be stored.

Claims

1. A memory controller comprising:

command logic to transmit a command that requests a memory device to store a plurality of data values; and

a packetizer to transmit to the memory device a data packet that includes a plurality of data values and a mask value, the mask value indicating respective locations within the memory device at which the plurality of data values are to be stored.

2. The memory controller of claim 1 wherein the mask value indicates respective locations within the memory device by indicating respective offsets from a base address.

3. The memory controller of claim 1 wherein at least a portion of the base address is indicated by the command.

4. The memory controller of claim 1, wherein the command logic comprises a state machine having a present state and a next state.

5. The memory controller of claim 4, wherein the state machine comprises:

a plurality of state storage elements to store the present state and the next state of the state machine; and

combinational logic to receive the mask value, a command, and the present state, the combination logic to determine the next state of the state machine based on the mask value, the command, and the present state.

6. The memory controller of claim 1, wherein the memory controller further comprises signaling logic coupled to the command logic, and wherein the command logic generates column command packets on a column control path by outputting successive sets of command bits.

7. The memory controller of claim 1, wherein the memory controller further comprises signaling logic coupled to the command logic, and wherein the command logic generates row command packets on a row control path by outputting successive sets of command bits.

8. The memory controller of claim 1, wherein the packetizer comprises:

a mask buffer to store the mask value;

a packet buffer having a plurality of entries; and

a logic circuit coupled to the packet buffer, the logic circuit coupled to receive the plurality of data values, the logic circuit to direct the plurality of data values and the mask value into particular entries of the plurality of entries based on the mask value.

9. The memory controller of claim 8, wherein the logic circuit comprises:

a plurality of multiplexers; and

packing logic coupled to the plurality of multiplexers to assert control signals to cause the mask value to be placed in one of the plurality of entries.

10. The memory controller of claim 8, wherein the plurality of data values are stored in the plurality of entries in a linear order if the mask value indicates that the data packet is to contain no masked values.

11. The memory controller of claim 8, wherein the mask value is stored in a first entry of the plurality of entries if any one of the plurality of entries is to be masked.

12. The memory controller of claim 8, further comprising:

data lines; and

signaling logic coupled to the data lines and the packetizer, the signaling logic to drive contents of the packet buffer onto the data lines.

13. A memory controller, comprising:

means for transmitting a command that requests a memory device to store a plurality of data values; and

means for transmitting to the memory device a data packet that includes a plurality of data values and a mask value, the mask value indicating respective locations within the memory device at which the plurality of data values are to be stored.

14. The memory controller of claim 13, further comprising means for packing the plurality of data values and the mask value into the data packet.

15. The memory controller of claim 14, further comprising means for driving the data packet onto a communication channel coupled to the memory device.

16. The memory controller of claim 13, further comprising means for driving the command onto a communication channel coupled to the memory device.

17. A method of information transmission, comprising:

receiving a plurality of data values;

receiving a mask value; and

packing the plurality of data values and the mask value into a data packet.

18. The method of claim 17, further comprising transmitting the data packet to a memory device.

19. The method of claim 18, wherein transmitting the data comprises driving the data packet onto a communication channel coupled to the memory device.

20. The method of claim 18, further comprising transmitting a command that requests the memory device to store the plurality of data values.

21. A memory controller, comprising:

a packet circuit to output to a memory device a packet that includes a plurality of values; and

a command circuit to output a command to request the memory device to store a subset of the plurality of values within the packet, the command to indicate whether the packet includes a mask value, the mask value to indicate storage locations within the memory device for some of the plurality of values.

22. The memory controller of claim 21, wherein the packet circuit comprises:

a mask buffer to store the mask value;

a packet buffer having a plurality of entries; and

a logic circuit coupled to the packet buffer, the logic circuit coupled to receive the plurality of values, the logic circuit to direct the plurality of values and the mask value into particular entries of the plurality of entries based on the mask value.

23. The memory controller of claim 22, wherein the command circuit comprises a state machine.