Dynamic semiconductor memory device

• US 6,151,244 A
• Filed: 10/21/1998
• Issued: 11/21/2000
• Est. Priority Date: 03/17/1998
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Arimoto, Kazutami, Fujino, Takeshi
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/176,029
• Time in Patent Office: 762 Days
• Field of Search: 365/149, 365/51, 365/63, 365/230.03
• US Class Current: 365/149
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Abstract

Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.

Claims

1. A semiconductor memory device comprising:

a plurality of word lines each arranged extending in a row direction and in parallel to others;

a plurality of first bit lines each arranged extending in a column direction and in parallel to others;

a plurality of one transistor/one capacitor type memory cells arranged corresponding to crossing of said plurality of word lines and said plurality of first bit lines, units of two memory cells arranged repeatedly in the column direction, two memory cells being placed opposite to each other relative to a bit line contact for making a contact with a corresponding first bit line, bit line contacts for adjacent bit lines being periodically positioned differently, and the bit line contacts being periodically positioned in the row direction with a plurality of bit lines being a unit, the bit line contacts and the memory capacitors being arranged in alignment in the row direction with the plurality of bit lines being the unit;

a plurality of cell plate lines individually provided corresponding to the first bit lines and coupled to cell plate nodes of the memory cells on the corresponding first bit lines for transferring cell plate potentials to the cell plate nodes of the memory cells of corresponding first bit lines, the cell plate node being a capacitor electrode of a memory capacitor of the memory cell facing to a data storage node of the memory cell; and

cell plate potential control circuit coupled to the cell plate lines for individually controlling the cell plate potentials on a cell plate line basis.

2. The semiconductor memory device according to claim 1, wherein the memory cell capacitors and the bit line contacts are arranged aligned between adjacent word lines.

3. The semiconductor memory device according to claim 1, wherein

the memory cells are arranged such that two memory cells for three of the first bit lines as a unit are arranged in said row direction, two memory cells for three word lines as a unit are arranged in said column direction, and the memory cells are arranged in different patterns between adjacent bit lines and between adjacent word lines.

4. A semiconductor memory device comprising:

a plurality of word lines each arranged extending in a row direction and in parallel to others;

a plurality of first bit lines each arranged extending in a column direction and in parallel to others;

a plurality of memory cells arranged corresponding to crossing of said plurality of word lines and said plurality of first bit lines, each memory cell being a one transistor/one capacitor type memory cell, units of two memory cells being placed opposite to each other relative to a bit line contact for making a contact with a corresponding first bit line, bit line contacts for adjacent bit lines being positioned differently and the bit line contacts being periodically positioned in the row direction with a plurality of bit lines being a unit,

wherein the memory cells are arranged such that two memory cells for three of the first bit lines as a unit are arranged in the row direction, two memory cells for three word lines as a unit are arranged in said column direction, and the memory cells are arranged in different patterns between adjacent bit lines and between adjacent word lines;

a plurality of cell plate lines individually provided corresponding to the first bit lines and coupled to cell plate nodes of the memory cells on the corresponding first bit lines for transferring cell plate potentials to the cell plate nodes of the memory cells of corresponding first bit lines, the cell plate node being a capacitor electrode of a memory capacitor of the memory cell facing to a data storage node of the memory cell; and

cell plate potential control circuit coupled to the cell plate lines for individually controlling the cell plate potentials on a cell plate line basis.

8. The semiconductor memory device according to claim 4, further comprising a plurality of second bit lines arranged alternately with the first bit lines, and a plurality of memory cells provided corresponding to said plurality of second bit lines respectively and arranged similarly to the memory cells corresponding to the first bit lines, wherein

said read inhibition circuitry includes means for controlling the bit line voltage and cell plate node voltage in a unit of adjacent first and second bit lines.

9. The semiconductor memory device according to claim 8, further comprising a plurality of second sense amplifiers placed on other side opposite to said one side of said plurality of first and second bit lines, the second provided one for three of the second bit lines, wherein

said sense amplifier select connect circuitry include means responsive to said row designation signal for implementing connection between said plurality of second bit lines and corresponding second sense amplifiers in a manner similar to a manner in which said plurality of first bit lines and said plurality of first sense amplifiers are connected.

5. A semiconductor memory device comprising:

a plurality of word lines, each arranged extending in a row direction and in parallel to others;

a plurality of first bit lines, each arranged extending in a column direction and in parallel to others; and

a plurality of memory cells arranged corresponding to crossings of said plurality of word lines and said plurality of first bit lines, each memory cell being a one transistor/one capacitor type memory cell, units of two memory cells being placed opposite to each other relative to a bit line contact for making a contact with a corresponding first bit line, bit line contacts for adjacent bit lines being positioned differently, and the bit line contacts being periodically positioned in the row direction with a plurality of bit lines being a unit,

a plurality of first sense amplifiers one provided for three of the first bit lines, the three first bit lines constituting a set;

a sense amplifier select connect circuit activated before a word line selection, for connecting two of said three first bit lines in each to a corresponding sense amplifier in accordance with a row designation signal;

a bit line potential control circuit activated before the word line selection and connected to each of the first bit lines, for setting a potential of one first bit line different from the two first bit lines connected to said corresponding sense amplifier in each of the sets to be higher than a prescribed voltage level in accordance with said row designation signal; and

a cell plate voltage control circuit activated before the word line selection, for setting potentials of cell plate nodes facing to data storage nodes of capacitors of memory cells respectively provided corresponding to one of said two first bit lines connected to said corresponding sense amplifier and to said one first bit line to be higher than said prescribed voltage in accordance with said row designation signal.

6. A semiconductor memory device comprising:

a plurality of word lines, each arranged extending in a row direction and in parallel to others;

a plurality of first bit lines, each arranged extending in a column direction and in parallel to others;

a plurality of memory cells arranged corresponding to crossings of said plurality of word lines and said plurality of first bit lines, each memory cell being a one transistor/one capacitor type memory cell, units of two memory cells being placed opposite to each other relative to a bit line contact for making a contact with a corresponding first bit line, bit line contacts for adjacent bit lines being positioned differently, and the bit line contacts being periodically positioned in the row direction with a plurality of bit lines being a unit;

a plurality of first sense amplifiers placed on one side of said plurality of first bit lines, said plurality of first sense amplifiers provided one for three of the first bit lines;

read inhibition circuitry for changing voltages, before a word line selection, to allow memory cell data to be read onto one of two first bit lines connected to memory cells on an addressed row and to inhibit reading of memory cell data onto the other of said two first bit lines in each set formed of the three first bit lines in accordance with a row designation signal, the voltages to be changed being a voltage of said the other of the two first bit lines and a voltage of a cell plate node facing to a data storage node of a memory cell connected to said the other of the two first bit lines; and

sense amplifier select connect circuitry for connecting said one of the two first bit lines and a remaining first bit line in each set of the first bit lines to a corresponding first sense amplifier in accordance with said row designation signal.

7. The semiconductor memory device according to claim 6, wherein

said sense amplifier select connect circuitry include means for connecting a specific one of the three first bit lines in each said set to a corresponding first sense amplifier or an adjacent first sense amplifier provided for an adjacent set.

10. A semiconductor memory device comprising:

a plurality of word lines extending in a row direction and arranged in parallel to each other;

a plurality of first bit lines extending in a column direction and arranged in parallel to each other; and

a plurality of first NAND type cells arranged in rows and columns each of the first NAND type cells having 2ⁿ one transistor/one capacitor type memory cells connected in series, wherein bit line contacts for contacting the first bit lines to said plurality of first NAND type cells are arranged at the same position in the row direction every first bit lines of a prescribed number of 2ⁿ or 2·

2ⁿ, and the bit line contacts are differently positioned for word lines adjacent to each other and for first bit lines adjacent to each other.

11. The semiconductor memory device according to claim 10, wherein

a unit structure formed of two of NAND type cells is repeatedly arranged in said column direction, said two of NAND type cells placed opposite to each other relative to a bit line contact for making a contact with a corresponding first bit line.

12. The semiconductor memory device according to claim 10, further comprising:

a plurality of first sense amplifiers arranged corresponding to respective sets each having a prescribed number of the first bit lines;

cell plate voltage control circuitry according to a row designation signal for setting voltage of a cell plate node of a capacitor of a memory cell connected to each of the first bit lines so as to allow memory cell data to be read onto one of the first bit lines of each of the sets and to inhibit reading of memory cell data onto remaining first bit lines of each of the sets, said voltage set individually for each of the first bit lines;

bit line voltage control circuitry for setting a voltage of each of the first bit lines individually according to said row designation signal so as to allow memory cell data to be read onto said one of the first bit lines in each of the sets and to inhibit reading of memory cell data onto remaining first bit lines in each of the sets; and

sense amplifier select connect circuitry responsive to said row designation signal for connecting the one first bit line in each of the sets and one of the remaining first bit lines in each of the sets to a corresponding one of the first sense amplifiers.

13. The semiconductor memory device according to claim 10, wherein

said bit line contacts are arranged to be shifted by a pitch of two word lines in the column direction in each of the sets.

14. The semiconductor memory device according to claim 12, further comprising:

second bit lines arranged alternately with said first bit lines; and

a plurality of second NAND type cells provided corresponding to the second bit lines and connected to corresponding second bit lines via bit line contacts arranged in an arrangement pattern similar to that of said plurality of first NAND type cells, wherein

cells connected to first and second bit lines adjacent to each other are provided with the same bit line contact arrangement pattern and share a cell plate voltage transmission line supplying a voltage to a cell plate node.

15. The semiconductor memory device according to claim 12, wherein

said bit line voltage control circuitry include means for controlling voltages of the second bit lines in a manner similar to that for controlling the voltages of the first bit lines in accordance with said row designation signal.

16. The semiconductor memory device according to claim 12, further comprising a plurality of second sense amplifiers arranged opposite to said plurality of first sense amplifiers relative to first and second bit lines and arranged corresponding to respective sets each having a prescribed number of second bit lines of said plurality of second bit lines, wherein

said sense amplifier select connect circuitry include means for implementing connection between the second bit lines and the second sense amplifiers in a manner similar to a manner in which the first sense amplifiers and the first bit lines are connected in accordance with said designation signal.