Multi-bit-per-cell flash EEPROM memory with refresh

• US 6,151,246 A
• Filed: 11/25/1998
• Issued: 11/21/2000
• Est. Priority Date: 09/08/1997
• Status: Expired due to Term

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: So, Hock C., Wong, Sau C.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/200,220
• Time in Patent Office: 727 Days
• Field of Search: 365/185.24, 365/185.25, 365/185.03, 365/184, 365/185.09, 371/21.4, 371/21.1
• US Class Current: 365/185.09
• CPC Class Codes: B64C 27/006 Safety devices
• CPC Class Codes: G01N 29/14 using acoustic emission techniques echo of particles G01N29/046; measuring mechanical vibrations or acoustic waves in solids in general G01H1/00
• CPC Class Codes: G01N 29/227 related to high pressure, tension or stress conditions
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.

Claims

1. A non-volatile semiconductor memory comprising:

an array of memory cells;

drivers and decoders coupled to apply voltages to the array to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage that identifies a multibit data value written in the memory cell;

an error detection circuit that detects errors in threshold voltages of memory cells storing data, wherein in response to detecting an error in the threshold voltage of a memory cell, the error detection circuit signals for a refresh operation; and

a control circuit coupled to control the drivers and decoders, wherein during the refresh operation, the control circuit writes a corrected threshold voltage that corrects the error that the error detection circuit detected.

2. The memory of claim 1, wherein the control circuit writes the corrected threshold voltage to the memory cell in which the error detection circuit detected the error.

3. The memory of claim 1, wherein the control circuit writes the corrected threshold voltage to a memory cell other than the memory cell in which the error detection circuit detected the error.

4. The memory of claim 3, further comprising an address mapping circuit that accounts for an address mapping, wherein when the control circuit writes the corrected threshold voltage to the other memory cell, the address mapping circuit changes the address mapping to indicate a new physical location for the corrected threshold voltage.

5. The memory of claim 1, wherein the control circuit reads refresh information for a sector containing the memory cell having the error in the threshold voltage and based on the refresh information selects where to write the corrected threshold voltage.

6. The memory of claim 1, wherein the control circuit reads a count of erase cycles for a sector containing the memory cell having the error in the threshold voltage and based on the count selects where to write the corrected threshold voltage.

7. The non-volatile memory of claim 1, wherein the error detection circuit comprises:

a reference generator that generates first reference signals and second reference signals, the first reference signals indicating bounds of ranges of threshold voltages allowed for the memory cells storing data, and the second reference signals indicating bounds of one or more ranges of threshold voltages forbidden for the memory cells storing data; and

a circuit that determines whether a threshold voltage of a memory cell is in one of the ranges allowed or one of the ranges forbidden.

8. The non-volatile memory of claim 1, wherein the error detection circuit processes an error detection code to identify a data error in data read from the array, the data error indicating the threshold voltage error in the memory cell.

9. The non-volatile memory of claim 1, further comprising a data correction circuit that processes an error correction code to identify the corrected threshold voltage.

10. A non-volatile semiconductor memory comprising:

an array of memory cells;

drivers and decoders coupled to apply voltages to the array to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage that identifies a multibit data value written in the memory cell;

a reference generator that generates first reference signals and second reference signals, wherein the first reference signals indicate bounds of ranges of threshold voltages allowed for the memory cells storing data, and the second reference signals indicate bounds of one or more ranges of threshold voltages forbidden for the memory cells storing data; and

a control circuit coupled to control the drivers and decoders during a refresh operation that reads a threshold voltage of a memory cell, detects whether the threshold voltage of the memory cell is in a range forbidden for memory cells storing data, and moves the threshold voltage of the memory cell into one of the ranges allowed for memory cells storing data.

11. The non-volatile memory of claim 10, further comprising a timer that periodically triggers the control circuit to start the refresh operation for at least a portion of the memory array.

12. The non-volatile memory of claim 11, wherein the array, the drivers and decoders, the reference generator, the control circuit, and the timer are parts of a monolithic integrated circuit.

13. The non-volatile memory of claim 11, further comprising a buffer coupled to temporarily store data from the portion of the memory array, during the refresh operation.

14. The non-volatile memory of claim 11, wherein a sector of the memory array temporarily stores data from the portion of the memory array, during the refresh operation.

15. The non-volatile memory of claim 10, wherein the ranges of threshold voltages allowed for memory cells storing data are separated from each other by at least one range of threshold voltages forbidden for memory cells storing data.

16. A non-volatile semiconductor memory comprising:

an array of memory cells;

drivers and decoders coupled to apply voltages to the array to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage that identifies a multibit data value written in the memory cell; and

a reference generator that generates signals indicate bounds of a plurality of ranges of threshold voltages allowed for the memory cells that store data, wherein each range in the plurality corresponds to a multibit value that differs in only a single bit from a multibit value corresponding to a range that is adjacent in threshold voltage.

17. The memory of claim 16, wherein the reference generator further generates reference signals indicating bounds of one or more ranges of threshold voltages forbidden for the memory cells storing data.

18. The memory of claim 17, further comprising a control circuit coupled to control the drivers and decoders, wherein during a refresh operation, the control circuit detects whether the threshold voltage of the memory cell is in a range forbidden for memory cells storing data, and sets the threshold voltage of a memory cell in the array into one of the ranges allowed for memory cells storing data.

19. The memory of claim 16, further comprising a control circuit coupled to control the drivers and decoders, wherein during a refresh operation, the control circuit detects whether data stored a memory cell contains a data error, uses a error correction code stored in the memory array to identify a correct data value for the memory cell, and sets the threshold voltage of a memory cell in the array into the range corresponding to the correct data value.

20. A method for operating a non-volatile memory, comprising:

writing a multibit digital value to a memory cell by programming a threshold voltage of the memory cell to level within a target range of threshold voltages, wherein the target range of threshold voltages is one of a plurality of first ranges of threshold voltages, each of the first ranges corresponding to a different multibit value;

measuring the threshold voltage of the memory cell;

identifying whether the threshold voltage is still in a range from the plurality of first ranges or is in a range from a second plurality of ranges of threshold voltages; and

in response to the threshold voltage being in the second plurality of threshold voltages, changing the threshold voltage so that the threshold voltage is in one of the first plurality of ranges of threshold voltages.

21. The method of claim 20, wherein changing the threshold voltage increases the threshold voltage so that the threshold voltage is in a nearest one of the first ranges.

22. The method of claim 20, wherein changing the threshold voltage decreases the threshold voltage so that the threshold voltage is in a nearest one of the first ranges.

23. The method of claim 20, wherein:

the plurality of first ranges of threshold voltages form a sequence of ranges ordered according to increasing maximum voltages;

each first range corresponds to a different multibit digital value; and

the multibit digital value for each range differs by only one bit, from the multibit value for the range immediately preceding in the series.