Asynchronous multiport register file with self resetting write operation

• US 6,151,266 A
• Filed: 10/03/1997
• Issued: 11/21/2000
• Est. Priority Date: 10/03/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Henkels, deceased, Walter Harvey, Joshi, Rajiv Vasant, Hwang, Wei
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/943,738
• Time in Patent Office: 1,145 Days
• Field of Search: 365/230.06, 365/189.08, 365/230.05, 365/230.08, 365/230.01
• US Class Current: 365/230.06
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Self-reset and write control circuits for high performance asynchronous multiport register files are disclosed. The high speed write operation is achieved by the combination of static data input and dynamic data control circuits. The write timing signal generation, true and complement address buffer, decoder and wordline drivers, and write enable circuits employ the advantages of a fully custom designed methodology with self-resetting complementary metal oxide semiconductor (SRCMOS) circuit techniques. Individual write enable pulses applied to respective input ports of a multiport register cell are effective to establish a priority among those input ports. In this design, the priority of the B-write-port over the A-write-port is established when both write ports address the same register. The present invention provides an effective input isolation/decoupling circuit technique which allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in effective input isolation scheme.

Claims

1. A write address macro for a register file, comprising:

input isolation circuit means for receiving first and second address signals and a global write enable signal and generating corresponding conditioned output signals of a predetermined duration;

a first write address buffer for receiving and temporarily storing the first conditioned write address signal from the input isolation circuit;

a second write address buffer for receiving and temporarily storing the second conditioned write address signal from the input isolation circuit;

a write decoder and write word line driver circuit coupled to receive the first and second conditioned write address signals from the first and second write address buffers, respectively, including means for generating true and complement word line select signals;

a write enable signal generator coupled to receive a conditioned write enable signal from the input isolation circuit means, including means for providing one or more write enable signals and a priority signal to the write decoder and write word line driver.

2. The macro of claim 1, wherein the inputs to the isolation circuit means are static, and wherein the outputs of the circuit are dynamic.

3. The macro of claim 2, wherein the input isolation circuit means comprises a first stage which receives the static input signal and performs a pulse chopping operation on the static input signal.

4. The macro of claim 3, wherein the first stage comprises a two-way NOR circuit.

5. The macro of claim 3, wherein the input isolation circuit further comprises a second stage, coupled to receive the output of the first stage, the second stage performing a pulse capture operation on the output of the first stage in the event that the output of the first stage is reset sooner than desired.

6. The macro of claim 5, wherein the second stage comprises a dynamic one-way NOR circuit.

7. The macro of claim 5, wherein the input isolator further comprises a third stage coupled to receive the output of the second stage, the third stage reducing the effects of noise on the output of the second stage, and also maintaining the output of the input isolator at a desired state during standby.

8. The macro of claim 7, wherein the third stage comprises a half-latch circuit.

9. The macro of claim 1, further comprising a write address timing circuit for generating and delivering respective write address timing signals to the first and second write address buffers.

10. The macro of claim 9, further comprising a write address timing signal input isolation circuit including means for receiving a global write address timing signal and generating a conditioned global write address timing signal for delivery to the write address timing circuit, the write address timing circuit generating the respective write address timing signals responsive to the conditioned global write address signal.

11. The macro of claim 1, further comprising a write enable signal input isolation circuit comprising means for receiving one or more global write enable signals and generating one or more corresponding conditioned global write enable signals for delivery to the write enable signal generator.

12. The macro of claim 11, wherein the write enable signal input isolation circuit comprises:

an input stage including means for performing a pulse-chopping operation on input pulses longer than a desired duration, said means including a static three-way NOR circuit;

a middle stage including means for capturing input pulses that are reset faster than desired, said means including a three-way AOI circuit;

an output stage including means for reducing the effects of noise on signals received from the second stage and for holding the output of the write enable signal isolation circuit in a predetermined state at standby, said means including a half-latch with feedback to a small standby device.

13. The macro of claim 1, wherein the first write address buffer includes a first stage comprising a four-way AOI circuit and a second stage, coupled to receive the output of the first stage, comprising a half latch circuit.

14. The macro of claim 1, wherein the second write address buffer includes:

a write port address buffer, the write port address buffer comprising a first stage that includes a one-way OR circuit, and a second stage, coupled to the output of the first stage, including a half-latch circuit, and

a true and complement address generating circuit coupled to the output of the output of the write port address buffer, including a pair of two-stage rails, each rail including a first stage comprising a two-way NAND circuit, and a second stage, coupled to the output of the first stage, including a half-latch circuit.

15. The macro of claim 1, wherein the write decoder and write word line driver circuit includes first and second 5-way NOR circuits for decoding the first and second conditioned write address signals from the first and second write address buffers, respectively, and a 2-way NAND coupled to receive the priority signal and the output of the 5-way NOR corresponding to the second write address signal to give priority to the writing of the second write address.

16. The macro of claim 1, further comprising a reset timing control circuit including means for generating and delivering timing and control signals to the input isolation circuit, first write address buffer, second write address buffer, write decoder and write word line driver, and write enable signal generator.