Pre-acquisition frequency offset removal in a GPS receiver

• US 6,151,353 A
• Filed: 06/26/1997
• Issued: 11/21/2000
• Est. Priority Date: 07/12/1996
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Harrison, Daniel David, Tiemann, Jerome Johnson
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): PARK, ALBERT C
• Application Number:
  US08/883,160
• Time in Patent Office: 1,244 Days
• Field of Search: 375/136, 375/140, 375/142, 375/147, 375/150, 342/352, 342/357, 342/378, 342/402, 342/417, 342/418, 342/419, 701/213
• US Class Current: 375/136
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G01S 19/42 Determining position
• CPC Class Codes: G01S 5/0027 of actual mobile position, i.e. position determined on mobile
• CPC Class Codes: G01S 5/0036 of measured values, i.e. measurement on mobile and position calculation on base station
• CPC Class Codes: G01S 5/0054 of actual mobile position, i.e. position calculation on base station
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/71075 Parallel interference cancellation
• CPC Class Codes: H04B 2201/70709 with discontinuous detection
• CPC Class Codes: H04W 52/0283 with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A direct sequence spread spectrum receiver samples an incoming signal and stores the sample in memory. Prior to sampling and storage, the incoming signal is translated to an IF signal. Also prior to storage, the IF signal is corrected for a frequency offset signal. The frequency offset may be caused by many sources, Doppler shift or local oscillator error, for example. Once the signal is corrected for the frequency offset, the signal sample is stored in memory. The signal sample is read from memory as necessary to process the signal. Such a receiver is useful in global positioning satellite (GPS) signal processing where the incoming signal contains several satellite transmissions encoded with CDMA encoding.

Claims

1. In a direct sequence spread spectrum receiver capable of receiving a plurality of signals from respective transmitters, apparatus comprising:

a tuner for receiving at least one of said signals and producing an intermediate frequency signal, said tuner including a converter for sampling said intermediate frequency signal;

means for removing frequency offset from the output signal of said converter, thereby producing a corrected signal;

a memory for storing said corrected signal; and

processing means for processing said corrected signal.

2. The receiver of claim 1, wherein:

said receiver is a GPS receiver and said transmitters are GPS satellite transmitters.

3. The receiver of claim 1, wherein:

said frequency offset comprises Doppler shift.

4. The receiver of claim 3, wherein:

said Doppler shift is known.

5. The receiver of claim 1, wherein:

said frequency offset comprises local oscillator error.

6. The receiver of claim 5, wherein:

said local oscillator error is known.

7. The receiver of claim 1, wherein:

said means for removing frequency offset from said received signal comprises a multiplier.

8. The receiver of claim 7, wherein said multiplier comprises a complex multiplier for multiplying I and Q output signals from said converter with I and Q Doppler frequency signals so as to provide II+QQ data and QI-IQ data to said memory.

9. The receiver of claim 8, wherein said memory comprises a first data-Doppler memory for storing said II and QQ data and a second data-Doppler memory for storing said QI-IQ data.

10. The receiver of claim 9 wherein said processing means comprises a first parallel correlation responsive to said first data-Doppler memory and a second parallel correlator responsive to said second data-Doppler memory.

11. The receiver of claim 1, wherein:

said processing means comprises a correlator.

12. The receiver of claim 11, wherein:

said correlator comprises a parallel correlator.

13. The receiver of claim 1, wherein,

a processing means is adapted to read said sample of said corrected signal as needed to process said sample.

14. In a direct sequence spread spectrum receiver capable of receiving a plurality of signals from respective transmitters, the method comprising:

receiving an input signal having a signal carrier frequency;

generating a local oscillator signal having frequency which is offset from said carrier frequency;

mixing said input signal with said local oscillator signal to produce an intermediate frequency signal;

converting said intermediate frequency signal to a multiple-sample digital representation thereof;

mixing said multiple-sample digital representation with a frequency offset signal to produce a corrected frequency signal;

storing said corrected frequency signal in a memory; and

processing said corrected frequency signal.

15. The method of claim 14, wherein:

said receiver is a GPS receiver and said transmitters are GPS satellite transmitters.

16. The method of claim 14, wherein:

said frequency offset signal comprises Doppler shift.

17. The method of claim 16, wherein:

said Doppler shift is known.

18. The method of claim 14, wherein:

said frequency offset signal comprises local oscillator error.

19. The method of claim 18, wherein:

said local oscillator error is known.

20. The method of claim 14, wherein:

the step of mixing said multiple-sample digital representation with a frequency offset signal comprises digital multiplication.

21. The method of claim 14, wherein:

said processing comprises correlation of said corrected frequency signal with a replica signal.

22. The method of claim 21, wherein:

said correlation comprises parallel correlation.

23. The method of claim 14, wherein,

said processing comprises reading said memory as needed to accomplish said processing.

24. The method of claim 14 wherein said multiple-sample digital representation comprises I and Q signals, and the step of mixing said multiple-sample digital representation with a frequency offset signal comprises complex digital multiplication.