Method and apparatus for phase detection in digital signals

• US 6,151,356 A
• Filed: 09/17/1998
• Issued: 11/21/2000
• Est. Priority Date: 04/28/1997
• Status: Expired due to Term

• Current Assignee: RPX Clearinghouse LLC (RPX Corporation)
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Foster, Stephen Richard, Sparks, Adrian Paul, Spagnoletti, Robert William
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Liu, Shuwang
• Application Number:
  US09/156,019
• Time in Patent Office: 796 Days
• Field of Search: 375/326, 375/354, 375/355, 375/360, 375/373, 375/376, 331/1 H, 331/2, 331/11, 395/551, 395/550, 327/12
• US Class Current: 375/226
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 25/063 Setting decision thresholds using feedback techniques only
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/046 using a dotting sequence
• CPC Class Codes: H04N 7/0352 for regeneration of the clock signal

Abstract

The invention provides an improved method and apparatus for detecting the phase difference between a digital data signal and a clock signal. By ensuring that no pulse in the output phase signal is narrow enough to introduce a non-linearity, the present invention avoids a source of non-linearity exhibited in existing phase detectors.

In addition, by ensuring that critical timing paths through the circuit contain similar circuit blocks, with similar propagation delays, relative time relationships are preserved from clock and data inputs to XOR inputs. The circuit is therefore largely insensitive to changes in the characteristics of the components so long as they all move together, as they would in an integrated circuit implementation.

Claims

1. A digital signal phase detector comprising:

a data signal input for receiving a data signal;

a clock signal input for receiving a clock signal;

a first circuit coupled to the data signal input and the clock signal input and arranged to provide a phase difference signal representative of both the clock period of the clock signal and the difference in phase between the clock signal and the data signal;

a second circuit coupled to the first circuit and arranged to provide a reference signal representative of the clock period of the clock signal and duration of whose pulses is dependent only on the clock period of the clock signal;

a third circuit coupled to receive the phase difference signal and responsive to extend by a predetermined amount the duration of signal pulses of the phase difference signal; and

wherein a comparison of the phase difference signal with the reference signal provides an indication of the phase difference between the clock signal and the data signal and an indication of the magnitude of said phase difference;

and wherein the indication of the magnitude of the phase difference between the clock signal and the data signal varies linearly with said phase difference.

2. A detector according to claim 1 wherein the phase difference signal and the reference signal are provided responsive to only the rising or only the falling state transitions in the received data signal.

3. A detector according to claim 1 wherein the predetermined amount is half a clock cycle.

4. A detector according to claim 1 wherein:

critical timing paths through the detector exhibit similar propagation delays.

5. A detector according to claim 1 comprising:

data-reduction circuit means arranged to provide a reduced data output signal which changes state upon receipt of either only rising or only falling state transitions in a digital input signal;

resynchronisation circuit means arranged to provide a resynchronised reduced data signal upon receipt of a clock input signal and the reduced data output signal;

first shift register circuit means arranged to provide a first phase-shifted resynchronised reduced data signal upon receipt of the resynchronised reduced data signal and one or more clock signals;

second shift register circuit means arranged to provide a second phase-shifted resynchronised reduced data signal upon receipt of the first phase-shifted resynchronised reduced data signal and one or more clock signals;

first Exclusive OR circuit means arranged to provide a phase difference signal upon receipt of the reduced data signal and the first phase-shifted resynchronised reduced data signal; and

second Exclusive OR circuit means arranged to provide a reference signal upon receipt of the resynchronised reduced data signal and the second phase-shifted resynchronised reduced data signal; and

whereby, in operation, the difference between the phase difference signal and the reference signal varies linearly with the difference in phase between the data signal and the clock signal received by the resynchronisation circuit means.

6. A detector according to claim 5, wherein the data-reduction circuit means is arranged to respond to all rising or all falling state transitions in the digital input signal.

7. A detector according to claim 5 wherein:

the data-reduction circuit means comprises a D-Type;

the resynchronisation circuit means comprises a D-Type;

the first shift register circuit means comprises a Latch;

the second shift register circuit means comprises a Latch;

the first XOR circuit means comprises an XOR gate; and

the second XOR circuit means comprises an XOR gate.

8. A detector according to claims 5, wherein the moving time average of the difference between the phase difference signal and the reference signal varies linearly with the difference in phase between the data signal and the clock signal received by the resynchronisation circuit.

9. A detector according to claim 5 additionally comprising:

integrating circuit means arranged to provide an integrated analogue signal which varies linearly with the phase difference between the data signal and the clock signal received by the resynchronisation circuit upon receipt of the phase difference signal and the reference signal.

10. A detector according to claim 5 additionally comprising:

integrating circuit means arranged to provide an integrated analogue signal the moving time average of which varies linearly with the phase difference between the data signal and the clock signal received by the resynchronisation circuit, in response to receipt of the phase difference signal and the reference signal.

11. A detector according to claim 1 arranged to receive clock signals from a multi-phase clock.

12. A detector according to claim 1 additionally comprising:

feedback circuit means arranged to provide a variable clock signal from which to derive the clock input signal, upon receipt of the phase difference signal and the reference signal; and

retiming circuit means arranged to provide a retimed data signal in response to receipt of the data signal and the variable clock signal.

13. A detector according to claim 1 additionally comprising:

feedback circuit means arranged to provide a variably-delayed data signal to be taken as the data signal received at the data signal input, upon receipt of the phase difference signal, the reference signal, and the data signal; and

retiming circuit means arranged to provide a retimed data signal upon receipt of the variably-delayed data signal and the clock signal.

14. A method of digital signal phase detection comprising the steps of:

providing a data signal;

providing a clock signal;

providing a phase difference signal responsive to and representative of both the clock period of the clock signal and the difference in phase between the clock signal and data signal;

providing a reference signal responsive to and representative of the clock period of the clock signal and duration of whose pulses is dependent only on the clock period of the clock signal;

extending by a predetermined amount the duration of the signal pulses of the phase difference signal; and

comparing the phase difference signal with the reference signal whereby to provide an indication of the phase difference between the clock signal and the data signal and an indication of the magnitude of said phase difference, which indication varies linearly with said phase difference.

15. The method of digital signal phase detection comprising the steps of:

provision of a reduced data digital output signal which changes state upon receipt of either only rising or only falling state transitions in a digital input signal;

resynchronisation to provide a resynchronised reduced data signal upon receipt of a clock input signal and the reduced data output signal;

phase-shifting to provide a first phase-shifted resynchronised reduced data signal upon receipt of the resynchronised reduced data signal and one or more clock signals;

phase-shifting to provide a second phase-shifted resynchronised reduced data signal upon receipt of the first phase-shifted resynchronised reduced data signal and one or more clock signals;

provision of a phase difference signal being the exclusive OR of the reduced data signal and the first phase-shifted resynchronised reduced data signal;

provision of a reference signal being the exclusive OR of the resynchronised reduced data signal and the second phase-shifted resynchronised reduced data signal; and

whereby the difference between the phase difference signal and the reference signal varies linearly with the difference in phase between the data signal and the clock signal used in resynchronisation.