Data transaction typing for improved caching and prefetching characteristics
First Claim
1. A microprocessor comprising:
- a decode unit coupled to receive an instruction and configured to determine a first data transaction type corresponding to said instruction, wherein said first data transaction type is one of a plurality of data transaction types; and
a load/store unit coupled to receive said first data transaction type if said instruction includes a memory operation, wherein said load/store unit is configured to determine an access mode for said memory operation in response to said first data transaction type, wherein said access mode comprises;
(i) a cacheability mode indicating whether or not data corresponding to said memory operation is cacheable, wherein said cacheability mode indicates non-cacheable for at least one of said plurality of data transaction types; and
(ii) a prefetch mode indicating a prefetch strategy corresponding to said memory operation.
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0 Petitions
Accused Products
Abstract
A microprocessor assigns a data transaction type to each instruction. The data transaction type is based upon the encoding of the instruction, and indicates an access mode for memory operations corresponding to the instruction. The access mode may, for example, specify caching and prefetching characteristics for the memory operation. The access mode for each data transaction type is selected to enhance the speed of access by the microprocessor to the data, or to enhance the overall cache and prefetching efficiency of the microprocessor by inhibiting caching and/or prefetching for those memory operations. Instead of relying on data memory access patterns and overall program behavior to determine caching and prefetching operations, these operations are determined on an instruction-by-instruction basis. Additionally, the data transaction types assigned to different instruction encodings may be revealed to program developers. Program developers may use the instruction encodings (and instruction encodings which are assigned to a nil data transaction type causing a default access mode) to optimize use of processor resources during program execution.
92 Citations
28 Claims
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1. A microprocessor comprising:
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a decode unit coupled to receive an instruction and configured to determine a first data transaction type corresponding to said instruction, wherein said first data transaction type is one of a plurality of data transaction types; and a load/store unit coupled to receive said first data transaction type if said instruction includes a memory operation, wherein said load/store unit is configured to determine an access mode for said memory operation in response to said first data transaction type, wherein said access mode comprises; (i) a cacheability mode indicating whether or not data corresponding to said memory operation is cacheable, wherein said cacheability mode indicates non-cacheable for at least one of said plurality of data transaction types; and (ii) a prefetch mode indicating a prefetch strategy corresponding to said memory operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for categorizing a memory operation comprising:
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decoding an instruction to determine a first data transaction type corresponding to said instruction, wherein said first data transaction type is one of a plurality of data transaction types; and accessing data corresponding to said instruction using an access mode responsive to said data transaction type, wherein said access mode comprises; (i) a cacheability mode indicating whether or not said data is cacheable, wherein said cacheability mode indicates non-cacheable for at least one of said plurality of data transaction types; and (ii) a prefetch mode indicating a prefetch strategy corresponding to said memory operation. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A microprocessor comprising:
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a decode unit coupled to receive an instruction and configured to determine a data transaction type corresponding to said instruction; and a load/store unit coupled to receive said data transaction type if said instruction includes a memory operation, wherein said load/store unit is configured to determine an access mode for said memory operation in response to said data transaction type, wherein said data transaction type comprises a pointer data transaction type indicating that said memory operation is a pointer access, wherein said access mode includes a non-cacheable indication indicating that data corresponding to said memory operation is non-cacheable. - View Dependent Claims (24)
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25. A method for categorizing a memory operation comprising:
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decoding an instruction to determine a data transaction type corresponding to said instruction, wherein said data transaction type comprises a pointer data transaction type; and accessing data corresponding to said instruction using an access mode responsive to said data transaction type, wherein said access mode comprises; (i) a cacheability mode indicating whether or not said data is cacheable; and (ii) a prefetch mode indicating a prefetch strategy corresponding to said memory operation, and wherein said cacheability mode indicates non-cacheable, and wherein said prefetch mode indicates prefetching using said data as a prefetch address.
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26. A computer system comprising:
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a microprocessor including; a decode unit coupled to receive an instruction and configured to determine a first data transaction type corresponding to said instruction, wherein said first data transaction type is one of a plurality of data transaction types; a load/store unit coupled to receive said first data transaction type if said instruction includes a memory operation, wherein said load/store unit is configured to determine an access mode for said memory operation in response to said first data transaction type, wherein said access mode comprises; (i) a cacheability mode indicating whether or not data corresponding to said memory operation is cacheable, wherein said cacheability indication indicates non-cacheable for at least one of said plurality of data transaction types; and (ii) a prefetch mode indicating a prefetch strategy corresponding to said memory operation; and an input/output (I/O) device configured to communicate between said computer system and another computer system to which said I/O device is capable of being coupled. - View Dependent Claims (27, 28)
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Specification