Anti-theft mechanism for mobile computers

• US 6,151,678 A
• Filed: 09/09/1997
• Issued: 11/21/2000
• Est. Priority Date: 09/09/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Davis, Derek L.
• Primary Examiner(s): Wright, Norman M.
• Application Number:
  US08/927,370
• Time in Patent Office: 1,169 Days
• Field of Search: 395/186, 395/188.01, 395/187.01, 713/200, 713/201, 714/47, 714/36, 714/48
• US Class Current: 726/35
• CPC Class Codes: G06F 21/305 by remotely controlling device operation
• CPC Class Codes: G06F 21/88 Detecting or preventing theft or loss
• CPC Class Codes: G06F 2211/1097 Boot, Start, Initialise, Power

Abstract

An electronic system that remains disabled after power-on until its user is recognized. The electronic system includes a host processor and a deactivation circuit coupled to the host processor. The deactivation circuit places the host processor into an inoperative state until the user is recognized. In one embodiment, the deactivation circuit is a security processor coupled to a reset input of the host processor. The security processor includes a processing unit and an internal memory unit to contain software required by the host processor to complete a booting procedure.

Claims

1. An electronic system comprising:

a host processor;

a power-on reset circuit; and

a deactivation circuit coupled to the host processor and the power-on reset circuit, the deactivation circuit to prevent the host processor from receiving instructions by continuously outputting an active reset signal to the host processor in response to a system power-on signal by the power-on reset circuit, the active reset signal places the host processor in an inoperative state until a user of the electronic system is recognized upon which the reset signal is deactivated.

2. The electronic system of claim 1, wherein the instructions include Basic Input/Output System (BIOS) instructions required during a boot procedure of the electronic system.

3. The electronic system of claim 1, wherein the deactivation circuit includes a security processor having a processing unit and an internal memory unit, the internal memory unit containing software used by the electronic system during a boot procedure.

4. The electronic system of claim 3, wherein the software contained within the internal memory unit includes Basic Input/Output System (BIOS) instructions.

5. The electronic system of claim 3, wherein the deactivation circuit further includes a signal line coupled to an output of the security processor and a Reset input of the host processor, the signal line, to transfer the reset signal.

6. The electronic system of claim 3, wherein the host processor fetches boot instructions from the security processor after the reset signal has been deactivated.

7. The electronic system of claim 1, wherein the deactivation circuit includes a security processor including

a logic integrated circuit;

a memory integrated circuit; and

a bus coupled to both the logic integrated circuit and the memory integrated circuit.

8. The electronic system of claim 7, wherein the memory integrated circuit contains at least one instruction needed for execution by the host processor during a boot procedure of the electronic system.

9. The electronic system of claim 7, wherein the security processor is placed in an operative state in response to the system power-on reset signal.

10. An electronic system comprising:

power means for transmitting a power-on reset signal at power-up of the electronic system;

processor means for executing a plurality of instructions; and

deactivation means for preventing the processor means from obtaining a plurality of boot instructions in response to receipt of the system power-on reset signal from the power means and for continuously providing an active reset signal that places the processor means in an inoperative state immediately after power-up of the electronic system until a user of the electronic system is recognized, the deactivation means being coupled to the processor means and the power means.

11. An electronic system comprising:

a host processor; and

a deactivation circuit coupled to the host processor, the deactivation circuit to (1) place the host processor in an inoperative state immediately after a system power-on reset signal is initiated in order to prevent the host processor from receiving any basic input output system (BIOS) instructions until a user of the electronic system is recognized by comparing the input data with data preloaded for use in identifying one or more authorized users, and (2) store BIOS instructions fetched by the host processor after the user is recognized.

12. The electronic system of claim 11, wherein the Basic Input/Output System (BIOS) instructions are required during a boot procedure of the electronic system.

13. A method for ensuring security of an electronic system, the method comprising:

placing a host processor in an inoperative state after power-on, which prevents the host processor from fetching any basic input output system (BIOS) instructions, by configuring a deactivation circuit to continuously output an active RESET signal to the host processor;

determining whether an intended user of the electronic system is recognized as an authorized user of the electronic system;

continuing to maintain the host processor in the inoperative state until the user is recognized as the authorized user; and

placing the host processor in an operative state when the user is recognized as the authorized user.

14. The method of claim 13, wherein the determining on whether the intended user is the authorized user includes:

receiving input data associated with the intended user; and

comparing the input data with character data of the authorized user provided prior to receiving the input data.

15. The method of claim 14, wherein the placing of the host processor in the operative state includes allowing access to a plurality of boot instructions by the host processor.

16. The method of claim 13, wherein the deactivation circuit includes a security processor and a power-on reset circuit, the power-on reset circuit signals the security processor to generate the active RESET signal in response to a power-up condition.

17. The method of claim 13, wherein the placing of the host processor in the operative state includes allowing the host processor to fetch BIOS instructions stored in the deactivation circuit.