Dynamic device power management

• US 6,151,681 A
• Filed: 06/22/1998
• Issued: 11/21/2000
• Est. Priority Date: 06/25/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Roden, Philip A., Neil, Patrick C., Rekieta, David W.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/102,245
• Time in Patent Office: 883 Days
• Field of Search: 713/500, 713/322, 713/600, 714/12, 709/248, 709/400
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power management method and system which includes providing a system having a plurality of clock operated circuits, each clock operated circuit being operable in response to the receipt of clock signals. A first subplurality of the clock operated circuits receives an uninterrupted stream of clock signals and thereby is uninterruptably operable and a second plurality of the clock operated circuits receives a normally off interruptable stream of clock signals and is normally inoperable. The system is sampled for the presence of data signals being input thereto. The clock signals are sent to the second plurality of circuits in response to the sampling the presence of data signals being input to the system to cause the second plurality of circuits to be operable. The data signals are transmitted to the second plurality of circuits after a time delay equal to or greater than the expired time from the sampling to the sending. The system can have a plurality of input/output terminals with the sampling comprising being at each of the input/output terminals. The system includes a clock for providing the clock signals and a decode logic for sampling at one of the input/output terminals and an arbiter circuit for sampling at the other input/output terminal.

Claims

1. A power management method which comprises the steps of:

(a) providing a system having a plurality of clock operated circuits, each of said clock operated circuits being operable in response to the receipt of clock signals, with a first subplurality of said clock operated circuits receiving an uninterrupted stream of clock signals from a first clock and thereby being uninterruptably operable and a second subplurality of said clock operated circuits receiving a normally off interruptible stream of clock signals from a second clock and being normally inoperable, wherein the first and second clocks are continuously synchronized in phase and have a common operating frequency;

(b) sampling said system for the presence of data signals being input to said system;

(c) sending said clock signals from said second clock to said second subplurality of circuits in response to the sampling the presence of data signals being input to said system to cause said second subplurality of circuits to be operable; and

(d) transmitting said data signals to said second subplurality of circuits after a time delay equal to or greater than the expired time from said step of sampling to said step of sending.

2. The method of claim 1 further including the step of providing a plurality of system input/output terminals, said step of sampling comprising the step of sampling at each of said input/output terminals.

3. The method of claim 1 wherein said system is provided with a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and a decode logic for said sampling, said decode logic providing a signal to said second clock responsive to said sampling the presence of data signals.

4. The method of claim 2 wherein said system is provided with a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and a decode logic for said sampling at one of said input/output terminals, said decode logic providing a signal to said second clock responsive to said sampling the presence of data signals.

5. The method of claim 1 wherein said system is provided with a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and an arbiter circuit for receiving an arbitration signal at said input to said system to be sampled, said arbiter circuit providing a signal to said second clock responsive to said receipt of said arbitration signal.

6. The method of claim 2 wherein said system is provided with a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and an arbiter circuit for receiving an arbitration signal at one of said input/output terminals to said system to be sampled, said arbiter circuit providing a signal to said second clock responsive to said receipt of said arbitration signal.

7. The method of claim 3 wherein said system is provided with a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and an arbiter circuit for receiving an arbitration signal at said input to said system to be sampled, said arbiter circuit providing a signal to said second clock responsive to said receipt of said arbitration signal.

8. The method of claim 4 wherein said system is provided with a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and an arbiter circuit for receiving an arbitration signal at one of said input/output terminals to said system to be sampled, said arbiter circuit providing a signal to said second clock responsive to said receipt of said arbitration signal.

9. A power management system which comprises:

(a) a system having a plurality of clock operated circuits, each of said clock operated circuits being operable in response to the receipt of clock signals, with a first subplurality of said clock operated circuits receiving an uninterrupted stream of clock signals from a first clock and thereby being uninterruptably operable and a second subplurality of said clock operated circuits receiving a normally off interruptible stream of clock signals from a second clock and being normally inoperable, wherein the first and second clocks are continuously synchronized in phase and have a common operating frequency;

(b) sampling circuitry for sampling said system for the presence of data signals being input to said system; and

(c) circuitry sending clock signals from said second clock to said second subplurality of circuits in response to the sampling the presence of data signals being input to said system to cause said second subplurality of circuits to be operable;

(d) said system including a time delay for transmitting said data signals to said second subplurality of circuits after said time delay equal to or greater than the expired time from said sampling to said sending.

10. The system of claim 9 further including a plurality of system input/output terminals, said sampling circuitry sampling at each of said input/output terminals.

11. The system of claim 9 further including a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and a decode logic for said sampling, said decode logic providing a signal to said second clock responsive to said sampling the presence of data signals.

12. The system of claim 10 wherein said system further includes a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and a decode logic for said sampling at one of said input/output terminals, said decode logic providing a signal to said second clock responsive to said sampling the presence of data signals.

13. The system of claim 9 wherein said system further includes a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and an arbiter circuit for receiving an arbitration signal at said input to said system to be sampled, said arbiter circuit providing a signal to said second clock responsive to said receipt of said arbitration signal.

14. The system of claim 10 wherein said system further includes a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and an arbiter circuit for receiving an arbitration signal at one of said input/output terminals to said system to be sampled, said arbiter circuit providing a signal to said second clock responsive to said receipt of said arbitration signal.

15. The system of claim 11 wherein said system further includes a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and an arbiter circuit for receiving an arbitration signal at said input to said system to be sampled, said arbiter circuit providing a signal to said second clock responsive to said receipt of said arbitration signal.

16. The system of claim 12 wherein said system further includes a first clock for providing said uninterrupted stream of clock signals, a second clock for providing said normally off interruptible stream of clock signals and an arbiter circuit for receiving an arbitration signal at one of said input/output terminals to said system to be sampled, said arbiter circuit providing a signal to said second clock responsive to said receipt of said arbitration signal.