Method of growing nitride semiconductors, nitride semiconductor substrate and nitride semiconductor device

• US 6,153,010 A
• Filed: 12/09/1998
• Issued: 11/28/2000
• Est. Priority Date: 04/11/1997
• Status: Expired due to Term

• Current Assignee: Nichia Corporation
• Original Assignee: Nichia Chemical Industries Limited (Nichia Corporation)
• Inventors: Nakamura, Shuji, Chocho, Kazuyuki, Kiyoku, Hiroyuki, Kozaki, Tokuya, Iwasa, Naruhito
• Primary Examiner(s): Utech, Benjamin L.
• Assistant Examiner(s): ANDERSON, MATTHEW A
• Application Number:
  US09/202,141
• Time in Patent Office: 720 Days
• Field of Search: 117/84, 117/88, 117/89, 117/91, 117/101, 117/102, 117/104, 117/105, 117/952, 117/95, 117/97, 117/106
• US Class Current: 117/95
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: C23C 16/042 using masks
• CPC Class Codes: C23C 16/303 Nitrides
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02642 Mask materials other than SiO2 or SiN
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01S 2301/173 : The laser chip comprising special buffer layers, e.g. dislocation prevention or reduction
• CPC Class Codes: H01S 2304/12 : Pendeo epitaxial lateral overgrowth [ELOG], e.g. for growing GaN based blue laser diodes
• CPC Class Codes: H01S 5/0213 : Sapphire, quartz or diamond based substrates
• CPC Class Codes: H01S 5/0422 : with n- and p-contacts on the same side of the active layer
• CPC Class Codes: H01S 5/2201 : in a specific crystallographic orientation
• CPC Class Codes: H01S 5/32025 : non-polar orientation
• CPC Class Codes: H01S 5/3211 : characterised by special cladding layers, e.g. details on band-discontinuities
• CPC Class Codes: H01S 5/3216 : quantum well or superlattice cladding layers
• CPC Class Codes: H01S 5/34333 : with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.

Claims

1. A nitride semiconductor growth method comprising the steps of:

(a) forming a nitride semiconductor layer on a support member including a dissimilar substrate made of a material different from a nitride semiconductor and having a major surface;

(b) forming a plurality of recess portions having bottom surfaces substantially parallel to an upper surface of the support member in said nitride semiconductor layer;

(c) selectively forming a first growth control mask on a top surface of the nitride semiconductor layer to selectively expose the nitride semiconductor layer from side surfaces of the recess portions; and

(d) growing a nitride semiconductor from an exposed surface of the nitride semiconductor layer by using a gaseous Group 3 element source and a gaseous nitrogen source.

2. A method according to claim 1, wherein the recess portions are formed by a plurality of individual grooves spaced apart from each other and extending parallel.

3. A method according to claim 2, wherein the plurality of individual grooves have a plurality of individual walls formed therebetween, and said first growth control mask is made up of individual stripes formed on top surfaces of the respective individual walls.

4. A method according to claim 3, wherein a total surface area of said first growth control mask is larger than that of bottom surfaces of the grooves.

5. A method according to claim 4, wherein a ratio of a width of each of the individual stripes to a width of each of the grooves is more than 1 and not more than 20.

6. A method according to claim 5, wherein each of the grooves has a depth of 500 angstroms to 5 μ

m.

7. A method according to claim 3, wherein the dissimilar substrate is a sapphire substrate having a major surface forming a (0001) plane, and the respective individual stripes extend in a direction perpendicular to a (1120) plane of sapphire.

8. A method according to claim 3, wherein the dissimilar substrate is a sapphire substrate having a major surface forming a (1120) plane, and the respective individual stripes extend in a direction perpendicular to the (1120) plane of sapphire.

9. A method according to claim 3, wherein the dissimilar substrate is a spinnel substrate having a major surface forming a (111) plane, and the respective stripes extend in a direction perpendicular to the (110) plane of spinnel.

10. A method according to claim 1, wherein the step (d) further comprises doping the nitride semiconductor portion with an n-type impurity during growth of the first nitride semiconductor portion.

11. A method according to claim 10, wherein the n-type impurity is added such that a doping concentration decreases with an increase in distance from the dissimilar substrate.

12. A method according to claim 1, wherein the gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio not more than 2,000.

13. A method according to claim 12, wherein the gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of not less than 10.

14. A method according to claim 12, wherein growth of the nitride semiconductor portion in the step (d) is performed by a metal organic vapor-phase epitaxial method.

15. A method according to claim 14, wherein growth of the nitride semiconductor portion is performed under a reduced pressure of 50 to 400 Torr.

16. A method according to claim 1, wherein the step (c) further comprises forming a second growth control mask on the bottom surfaces of the recess portions to selectively expose the nitride semiconductor layer from side surfaces of the recess portions.

17. A method according to claim 16, wherein the recess portions are formed by a plurality of individual grooves spaced apart from each other and extending parallel.

18. A method according to claim 17, wherein the plurality of individual grooves have a plurality of individual walls formed therebetween, and said first growth control mask is made up of individual stripes formed on top surfaces of the respective individual walls.

19. A method according to claim 18, wherein a portion of the nitride semiconductor layer that is exposed from a side surface of the recess portion has a thickness of not less than 100 angstroms.

20. A method according to claim 18, wherein a portion of the nitride semiconductor layer that is exposed from a side surface of the recess portion has a thickness of 1 to 10 μ

m.

21. A method according to claim 18, wherein the dissimilar substrate is a sapphire substrate having a major surface forming a (0001) plane, and the respective individual stripes extend in a direction perpendicular to a (1120) plane of sapphire.

22. A method according to claim 18, wherein the dissimilar substrate is a sapphire substrate having a major surface forming a (1120) plane, and the respective individual stripes extend in a direction perpendicular to the (1120) plane of sapphire.

23. A method according to claim 18, wherein the dissimilar substrate is a spinnel substrate having a major surface forming a (111) plane, and the respective stripes extend in a direction perpendicular to the (110) plane of spinnel.

24. A method according to claim 16, wherein the step (d) further comprises doping the nitride semiconductor portion with an n-type impurity during growth of the first nitride semiconductor portion.

25. A method according to claim 24, wherein the n-type impurity is added such that a doping concentration decreases with an increase in distance from the dissimilar substrate.

26. A method according to claim 16, wherein the gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of not more than 2,000.

27. A method according to claim 26, wherein the gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of not less than 10.

28. A method according to claim 27, wherein growth of the nitride semiconductor portion is performed under a reduced pressure of 50 to 400 Torr.

29. A method according to claim 26, wherein growth of the nitride semiconductor portion in the step (d) is performed by a metal organic vapor-phase epitaxial method.

30. A nitride semiconductor growth method characterized by comprising the steps of forming a nitride semiconductor on a support member including a dissimilar substrate, using said nitride semiconductor as a seed crystal to grow a new nitride semiconductor in substantially only a lateral direction while suppressing growth of the nitride semiconductor in a vertical direction, and then growing the nitride semiconductor in both the vertical and lateral directions, thereby obtaining an integral nitride semiconductor crystal on a substantially entire upper surface of the support member.