Semiconductor device manufacturing method

• US 6,153,448 A
• Filed: 08/20/1999
• Issued: 11/28/2000
• Est. Priority Date: 05/14/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Katsumata, Akio, Takahashi, Takuya
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Parekh, Nitin
• Application Number:
  US09/377,864
• Time in Patent Office: 466 Days
• Field of Search: 257/738, 257/737, 257/780, 257/781, 257/786, 438/113, 438/612, 438/613, 438/666, 438/462, 438/465
• US Class Current: 438/114
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/484 : Connecting portions
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10157 : at the active surface

Abstract

There is provided a semiconductor device having a chip-size package structure comprising a semiconductor pellet including semiconductor elements, wires, a plurality of electrode pads, and final protection film, an insulation layer serving also as a sealing layer formed to cover the entire surface of the semiconductor pellet having a via hole portion above each of the electrode pads in association therewith, a plurality of wiring patterns formed with a via hole wiring portion electrically connected to the electrode pad at the bottom of each of the via hole portions of the insulation layer and formed with a land portion connected thereto and located in a position offset from the via hole portion, and an external electrode in the form of a ball provided on the land portion of each of the wiring patterns. This makes it possible to provide a semiconductor device in a chip-size package structure in which the length of wires led out from electrode pads is shortened as much as possible to lead out wires from electrode pads near the center of the pellet easily and to allow a pellet having an increased number of external electrodes to be accommodated.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a plurality of chip regions including a plurality of electrode pads on a semiconductor wafer;

forming a barrier metal layer on said semiconductor wafer and performing etching to selectively leave the barrier metal on the electrode pad in each of said chip region and in a predetermined region surrounding the same;

forming line grooves to a depth which is halfway the thickness of the substrate between the chip regions of said semiconductor wafer;

forming an insulation layer serving also as a sealing layer having openings for via holes in correspondence to the arrangement of said barrier metal;

forming wiring patterns including via hole wiring portions connected to said barrier metal at the bottom of said openings for via holes and including land portions connected thereto and arranged regularly in the form of a matrix in positions on the tape insulation layer offset from said via hole portions;

mounting external electrodes in the form of balls on the land portions of said wiring patterns; and

cutting the wafer with a dicing saw along the center lines of said line grooves to divide it into semiconductor devices in a chip-size package structure including a ball grid array electrode.

2. A method for manufacturing a semiconductor device according to claim 1, wherein at said step of forming the insulation layer serving also as a sealing layer, a thermally hardened epoxy tape formed with said openings for via holes using a punching process is applied to said semiconductor wafer using a thermo-compression bonding process.

3. A method for manufacturing a semiconductor device according to claim 2, wherein a metal core material is added to said thermally hardened epoxy tape.

4. A method for manufacturing a semiconductor device according to claim 1, wherein at said step of forming the insulation layer serving also as a sealing layer, said semiconductor wafer is coated with a liquid material such as photosensitive epoxy and, thereafter, patterning is performed using a photolithographic process to form said openings for via holes.

5. A method for manufacturing a semiconductor device according to claim 1, wherein at said step of the wiring patterns, an electroless plating process is performed to plate the entire surface of said semiconductor wafer with Cu and etching is performed using a photolithographic process to leave predetermined Cu patterns and, thereafter, an electrolytic process is performed to form a metal layer made of Au and Ni on the Cu patterns.