JFET transistor manufacturing method

• US 6,153,453 A
• Filed: 03/30/1999
• Issued: 11/28/2000
• Est. Priority Date: 03/31/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Jimenez, Jean
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Lee, Hsien Ming
• Application Number:
  US09/281,454
• Time in Patent Office: 609 Days
• Field of Search: 438/199, 438/197, 438/200, 438/188, 438/189, 438/196, 438/186, 438/201, 438/217, 438/211, 438/230, 438/231, 438/232, 438/299, 438/300, 438/305, 438/306, 257/133, 257/134, 257/272, 257/369
• US Class Current: 438/200
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 27/085 including field-effect components only

Abstract

The present invention relates to a method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in an N-type well of a P-type substrate, including the steps of forming a P-type channel region at the same time as lightly-doped drain/source regions of the P-channel MOS transistors of; forming an N-type gate region at the same time as lightly-doped drain/source regions of the N-channel MOS transistors; and forming P-type drain/source regions at the same time as heavily-doped drain/source regions of P-channel MOS transistors of channel.

Claims

1. A method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in a well of a first conductivity type of a substrate of the second conductivity type, including the steps of:

forming a JFET channel region of the second conductivity type at the same time as lightly-doped drain/source regions of the second conductivity type-channel MOS transistors;

forming a JFET gate region of the first conductivity type at the same time as lightly-doped drain/source regions of the first conductivity type-channel MOS transistors; and

forming JFET drain/source regions of the second conductivity type at the same time as heavily-doped drain/source regions of second conductivity type-channel MOS transistors.

2. The method of claim 1, wherein the substrate is doped at a 10¹⁴ at./cm³ dose, the well is doped at 10¹⁶ at./cm³, the JFET channel region is doped at a 10¹⁸ at./cm³ dose, the JFET gate region is doped at 10²⁰ at./cm³, and the JFET drain/source regions are doped at 10²⁰ at./cm³.

3. A method of manufacturing a first conductivity type-channel JFET transistor in a substrate of the second conductivity type of an integrated circuit containing complementary MOS transistors, including the steps of:

forming a channel region of the first conductivity type at the same time as anti-punch through regions of the second conductivity type-channel MOS transistors;

forming a gate region of the second conductivity type at the same time as lightly-doped drain/source regions of the second conductivity type-channel MOS transistors; and

forming drain/source regions of the first conductivity type at the same time as heavily-doped drain/source regions of the first conductivity type-channel MOS transistors.

4. The method of claim 3, wherein the substrate is doped at a 10¹⁴ at./cm³ dose, its channel region of the first conductivity type-channel JFET transistor is doped at a dose from 10¹⁷ at./cm³ to 10¹⁸ at./cm³, its gate region is doped at 10²⁰ at./cm³, and its drain/source regions are doped at 10²⁰ at./cm³.