Method of fabricating high density buried bit line flash EEPROM memory cell with a shallow trench floating gate

• US 6,153,467 A
• Filed: 03/18/1999
• Issued: 11/28/2000
• Est. Priority Date: 06/03/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wu, Shye-Lin
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Hack, Jonathan
• Application Number:
  US09/271,736
• Time in Patent Office: 621 Days
• Field of Search: 438/257, 438/221, 438/222, 438/259, 438/262, 438/26, 438/270, 438/280, 438/263
• US Class Current: 438/257
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps. Firstly, a pad oxide layer and a conductive impurity (such as phosphorus) doped polysilicon layer is successively formed on the silicon substrate. Then, an oxidation process is performed to oxidize the polysilicon layer and to drive in the conductive impurities. After coating a patterned mask on the resultant surface to define a plurality of buried bit line regions, a dry etch is used to etch away the unmask regions till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and a gate dielectric layer, such as gate nitride or oxynitride layer is formed on the resultant surface. After refilling a plurality of trenches with a conductive impurity doped silicon layer, a planarization process such as CMP is followed to form a plain surface using the gate dielectric layer as an etching stopped layer. A stacked ONO layer is then deposited as an interpoly dielectric layer; and finally another a conductive impurity doped polysilicon layer is formed and patterned to be as word lines.

Claims

1. A method of fabricating buried bit line flash EEPROM with a trench floating gate, comprising the steps of:

forming a pad oxide layer on a silicon substrate;

forming a first polysilicon layer with conductivity type impurities on said pad oxide layer;

oxidizing said first polysilicon layer so as to form an oxide layer on said pad oxide and driving said conductivity type impurities through said pad oxide layer so as to form a conductive silicon layer with said conductivity type impurities therein, which is beneath said pad oxide layer;

coating a patterned mask on said oxide layer to define a plurality of buried bit line regions;

forming a plurality of trenches come down into said silicon substrate using said patterned mask as a mask and defined said buried bit lines by utilizing said conductive silicon layer;

removing said patterned mask;

forming a gate dielectric layer on said plurality of trenches and form forming a silicon layer to refill said plurality of trenches;

performing a planarization process to a resultant surface to form a plain surface using said gate dielectric layer as an etching stopping layer;

forming an interpoly dielectric layer on a resultant surfaces; and

forming a polysilicon layer on said interpoly dielectric layer to define word lines.

2. The method of claim 1, wherein said step of forming a first polysilicon layer with conductive impurities is formed at a temperature of about a temperature of about 400 to 620°

C. to about . . . a thickness of about 10-100 nm.

3. The method of claim 1, wherein said first polysilicon layer is formed by a method selected from the group consisting of a in-situ doped CVD process, CVD process followed by a pocl doped process, and a CVD process followed by ion implant.

4. The method of claim 1, wherein said steps of oxidizing said polysilicon is implemented at a temperature of about 400-620°

C.

5. The method of claim 1, wherein said gate dielectric layer is a nitride layer with a thickness of about 2-30 nm formed by selecting a measure consisting from the group consisting of a CVD process and a LPCVD process.

6. The method of claim 5, after forming said nitride layer further comprising an oxidation process so as to transformed said nitride layer to an oxynitride layer, said oxidation process is done at a temperature about 800-1150°

C. in an ambient N₂ O/NO.

7. The method of claim 6, wherein said step of recessing said oxide layer, pad oxide layer and silicon layer is performed by a dry etching method.

8. The method of claim 7, wherein said of plurality trenches are with depths of about 50-600 nm each, which is measured from the upper surface of said silicon substrate to the bottom of each said trench.

9. The method of claim 1, wherein said silicon layer comprises amorphous silicon and polysilicon layer, and contains n-type dopants to concentrations of about 5×

10¹⁹ -5×

10²¹ /cm³.

10. The method of claim 1, wherein said steps of forming silicon layer is done at a temperature of about 450-650°

C.

11. The method of claim 1, wherein said step of performing a planarization process is done by a method comprising a CMP process.

12. The method of claim 1, wherein said interpoly dielectric layer is a stacked ONO layer, said ONO is with a second oxide layer over a nitride layer/first oxide layer to about 1-5 nm, 4-20 nm, and 1-5 nm, respectively.

13. The method of claim 1, wherein said step of forming polysilicon layer is performed by a LPCVD method at a temperature of about 450-650°

C., and with n-type doping concentrations of about 5×

10¹⁹ -5×

10²¹ /cm³.

14. The method of claim 1, wherein said conductive type impurities are selected from the group consisting of arsenic containing dopants and phosphorus containing dopants.