Method of fabricating high density buried bit line flash EEPROM memory cell with a shallow trench floating gate
First Claim
1. A method of fabricating buried bit line flash EEPROM with a trench floating gate, comprising the steps of:
- forming a pad oxide layer on a silicon substrate;
forming a first polysilicon layer with conductivity type impurities on said pad oxide layer;
oxidizing said first polysilicon layer so as to form an oxide layer on said pad oxide and driving said conductivity type impurities through said pad oxide layer so as to form a conductive silicon layer with said conductivity type impurities therein, which is beneath said pad oxide layer;
coating a patterned mask on said oxide layer to define a plurality of buried bit line regions;
forming a plurality of trenches come down into said silicon substrate using said patterned mask as a mask and defined said buried bit lines by utilizing said conductive silicon layer;
removing said patterned mask;
forming a gate dielectric layer on said plurality of trenches and form forming a silicon layer to refill said plurality of trenches;
performing a planarization process to a resultant surface to form a plain surface using said gate dielectric layer as an etching stopping layer;
forming an interpoly dielectric layer on a resultant surfaces; and
forming a polysilicon layer on said interpoly dielectric layer to define word lines.
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Abstract
A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps. Firstly, a pad oxide layer and a conductive impurity (such as phosphorus) doped polysilicon layer is successively formed on the silicon substrate. Then, an oxidation process is performed to oxidize the polysilicon layer and to drive in the conductive impurities. After coating a patterned mask on the resultant surface to define a plurality of buried bit line regions, a dry etch is used to etch away the unmask regions till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and a gate dielectric layer, such as gate nitride or oxynitride layer is formed on the resultant surface. After refilling a plurality of trenches with a conductive impurity doped silicon layer, a planarization process such as CMP is followed to form a plain surface using the gate dielectric layer as an etching stopped layer. A stacked ONO layer is then deposited as an interpoly dielectric layer; and finally another a conductive impurity doped polysilicon layer is formed and patterned to be as word lines.
29 Citations
14 Claims
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1. A method of fabricating buried bit line flash EEPROM with a trench floating gate, comprising the steps of:
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forming a pad oxide layer on a silicon substrate; forming a first polysilicon layer with conductivity type impurities on said pad oxide layer; oxidizing said first polysilicon layer so as to form an oxide layer on said pad oxide and driving said conductivity type impurities through said pad oxide layer so as to form a conductive silicon layer with said conductivity type impurities therein, which is beneath said pad oxide layer; coating a patterned mask on said oxide layer to define a plurality of buried bit line regions; forming a plurality of trenches come down into said silicon substrate using said patterned mask as a mask and defined said buried bit lines by utilizing said conductive silicon layer; removing said patterned mask; forming a gate dielectric layer on said plurality of trenches and form forming a silicon layer to refill said plurality of trenches; performing a planarization process to a resultant surface to form a plain surface using said gate dielectric layer as an etching stopping layer; forming an interpoly dielectric layer on a resultant surfaces; and forming a polysilicon layer on said interpoly dielectric layer to define word lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification