Advanced methods for making semiconductor devices by low temperature direct bonding

• US 6,153,495 A
• Filed: 03/09/1998
• Issued: 11/28/2000
• Est. Priority Date: 03/09/1998
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation), the united states of america as represented by the secretary of the navy
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Kub, Francis J., Temple, Victor, Hobart, Karl, Neilson, John
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US09/036,815
• Time in Patent Office: 995 Days
• Field of Search: 438/58, 438/143, 438/310, 438/406, 438/455, 438/459, 438/471, 438/473, 438/474, 438/477, 438/795, 438/977
• US Class Current: 438/459
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66363 Thyristors
• CPC Class Codes: H01L 29/66424 Permeable base transistors [PBT]
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method for making a semiconductor device from a plurality of semiconductor substrates includes the steps of: processing at least one surface of at least one of the substrates; thinning at least one of the substrates; bonding the processed and thinned substrates together so that the at least one processed surface defines an outer surface of the semiconductor device; and annealing the bonded together substrates at a relatively low anneal temperature so as to not adversely effect the at least one processed surface. The step of thinning preferably comprises removing a surface portion of the least one substrate opposite the processed surface, to a thickness of less than about 200 μm. A gettering layer may be formed for the at least one substrate prior to thinning. Accordingly, the step of thinning removes the gettering layer. An implanted region may be formed at a surface of the at least one substrate opposite the processed surface prior to bonding. The implanting may comprise implanting with a lifetime killing implant or a dopant. An epitaxial layer may be formed on the backside of a substrate. The step of processing may include forming a metal layer. Thus, the anneal temperature is preferably less than a temperature related to a characteristic of the metal layer. For an aluminum layer, the anneal temperature is preferably less than about 450° C. If a barrier metal is used between the aluminum and substrate, the anneal temperature may be in a range of about 450 to 550° C.

Claims

1. A method for making a semiconductor circuit from a plurality of semiconductor substrates, the method comprising the steps of:

processing at least one surface of at least one of the substrates to form at least one active device of the semiconductor circuit;

thinning at least one of the substrates;

bonding the plurality of substrates together after the processing and thinning steps so that the at least one processed surface including the at least one active device defines an outer surface of the semiconductor circuit; and

annealing the bonded together substrates at an anneal temperature so as to not adversely effect the at least one active device.

2. A method according to claim 1 wherein the step of thinning comprises removing a surface portion of the least one substrate opposite the processed surface.

3. A method according to claim 1 wherein the step of thinning comprises thinning to a thickness of less than about 200 μ

m.

4. A method according to claim 1 further comprising the step of polishing the thinned surface to a predetermined surface roughness.

5. A method according to claim 1 further comprising the step of forming a gettering layer for the at least one substrate prior to thinning;

and wherein the step of thinning comprises removing the gettering layer.

6. A method according to claim 5 wherein the step of forming the gettering layer comprises performing at least one of a phosphorous diffusion, an ion implantation of argon or carbon, and polysilicon deposition.

7. A method according to claim 5 wherein the step of forming the gettering layer comprises forming same prior to the processing step.

8. A method according to claim 1 further comprising the step of forming an implanted region at a surface of the at least one substrate opposite the processed surface prior to bonding.

9. A method according to claim 8 wherein the step of implanting comprises implanting with a lifetime killing implant.

10. A method according to claim 9 wherein the step of implanting comprises implanting in a predetermined pattern to define a plurality of laterally spaced lifetime killing implant regions.

11. A method according to claim 9 wherein the lifetime killing implant comprises at least one of protons, helium, carbon, oxygen, argon, silicon, platinum, palladium, gold, iron and nickel.

12. A method according to claim 1 further comprising the step of forming a doped layer at a surface of the at least one substrate opposite the processed surface prior to bonding.

13. A method according to claim 12 wherein the step of forming the doped layer comprises implanting a dopant into the surface.

14. A method according to claim 13 wherein the at least one substrate has a first conductivity type dopant;

and wherein step of implanting a dopant comprises implanting a dopant of a second conductivity type into the doped layer at a concentration greater than a concentration of the first dopant in the substrate.

15. A method according to claim 14 further comprising the step of activating the implanted dopant.

16. A method according to claim 12 wherein the step of forming the doped layer comprises forming an epitaxial doped layer.

17. A method according to claim 1 further comprising the step of forming an epitaxial layer at a surface of the at least one substrate opposite the processed surface prior to bonding.

18. A method according to claim 17 wherein the at least one substrate comprises silicon and the epitaxial layer comprises germanium.

19. A method according to claim 1 wherein the step of processing comprises forming a highly doped buffer layer of a first conductivity type on a doped substrate of the first conductivity type.

20. A method according to claim 1 wherein the step of processing comprises implanting a highly doped buffer layer of a first conductivity type in a doped substrate of the first conductivity type.

21. A method according to claim 1 wherein the step of bonding is carried out in a vacuum.

22. A method according to claim 1 further comprising the step of mounting at least one of the substrates to be thinned onto a handling substrate prior to thinning.

23. A method according to claim 1 further comprising the step of aligning the substrates prior to bonding.

24. A method according to claim 23 wherein the step of aligning comprises:

defining predefined corresponding portions in each substrate;

cutting the substrates along the predefined portions to define cut edges; and

aligning the substrates along the cut edges.

25. A method according to claim 23 further comprising the step of testing individual devices on each substrate, and aligning the substrates to increase a yield of the devices.

26. A method according to claim 1 wherein the step of processing comprises forming a metal layer;

and wherein the anneal temperature is less than a temperature related to a characteristic of the metal layer.

27. A method according to claim 1 wherein the step of processing comprises forming an aluminum layer;

and wherein the anneal temperature is less than about 450°

C.

28. A method according to claim 1 wherein the step of processing comprises forming an aluminum layer, and forming a barrier metal between the aluminum layer and substrate;

and wherein the anneal temperature is in a range of about 450 to 550°

C.

29. A method according to claim 1 wherein the step of processing comprises forming at least doped region;

further comprising the step of forming at least one metal layer after the annealing step; and

wherein the anneal temperature is less than about 800°

C.

30. A method according to claim 1 wherein the anneal temperature is greater than about 400°

C.

31. A method according to claim 1 wherein the step of annealing comprises annealing for a predetermined time.

32. A method according to claim 1 wherein the substrates comprise silicon;

and further comprising the step of hydrogen terminating silicon surfaces prior to the bonding step.

33. A method according to claim 1 further comprising the step of cleaning surfaces to be bonded of at least one of hydrocarbons and metals.

34. A method according to claim 1 wherein the at least one active device comprises at least one MOSFET control device.

35. A method according to claim 1 wherein the plurality of substrates is two;

and wherein the processing step comprises processing both substrates.

36. A method according to claim 1 wherein the step of bonding comprises bonding at a predetermined temperature in a predetermined ambient, and with a predetermined pressure.

37. A method according to claim 1 wherein the step of annealing comprises annealing in a predetermined ambient, and with a predetermined pressure.

38. A method for making a semiconductor circuit from a plurality of semiconductor substrates, the method comprising the steps of:

forming a gettering layer for at least one of the substrates;

processing at least one surface of at least one of the substrates to form at least one active device of the semiconductor circuit;

thinning at least one of the substrates and thereby removing the at least one gettering layer;

bonding the plurality of substrates together after the processing and thinning steps so that the at least one processed surface including the at least one active device defines an outer surface of the semiconductor circuit; and

annealing the bonded together substrates at an anneal temperature so as to not adversely effect the at least one active device.

39. A method according to claim 38 wherein the step of forming the gettering layer comprises performing at least one of a phosphorous diffusion, an ion implantation of argon, silicon, oxygen, or carbon, and polysilicon deposition.

40. A method according to claim 39 wherein the step of forming the gettering layer comprises forming same prior to the processing step.

41. A method according to claim 38 wherein the step of processing comprises forming a metal layer;

and wherein the anneal temperature is less than a temperature related to a characteristic of the metal layer.

42. A method according to claim 38 wherein the step of processing comprises forming an aluminum layer;

and wherein the anneal temperature is less than about 450°

C.

43. A method according to claim 38 wherein the step of processing comprises forming an aluminum layer, and forming a barrier metal between the aluminum layer and substrate;

and wherein the anneal temperature is in a range of about 450 to 550°

C.

44. A method according to claim 38 wherein the step of processing comprises forming at least doped region;

further comprising the step of forming at least one metal layer after the annealing step; and

wherein the anneal temperature is less than about 800°

C.

45. A method according to claim 38 wherein the anneal temperature is greater than about 400°

C.

46. A method according to claim 38 wherein the step of processing comprises completely processing the at least one substrate to form all active devices and interconnections.

47. A method according to claim 38 wherein the at least one active device comprises at least one MOSFET control device.

48. A method for making a semiconductor circuit from a plurality of semiconductor substrates, the method comprising the steps of:

processing at least one surface of at least one of the substrates to form at least one active device of the semiconductor circuit;

implanting a region of at least one substrate opposite the processed surface;

bonding the plurality of substrates together after the processing and thinning steps so that the at least one processed surface including the at least one active device defines an outer surface of the semiconductor circuit; and

annealing the bonded together substrates at an anneal temperature so as to not adversely effect the at least one active device and the implanted region.

49. A method according to claim 48 further comprising the step of thinning at least one of the substrates prior to the bonding step.

50. A method according to claim 48 wherein the step of implanting comprises implanting with a lifetime killing implant.

51. A method according to claim 50 wherein the step of implanting comprises implanting in a predetermined pattern to define a plurality of laterally spaced lifetime killing implant regions.

52. A method according to claim 51 wherein the lifetime killing implant comprises at least one of protons, helium, carbon, oxygen, argon, silicon, platinum, palladium, gold, iron and nickel.

53. A method according to claim 48 wherein the step of implanting comprises implanting a dopant into the surface.

54. A method according to claim 53 wherein the at least one substrate has a first conductivity type dopant;

and wherein step of implanting a dopant comprises implanting a dopant of a second conductivity type into the doped layer at a concentration greater than a concentration of the first dopant in the substrate.

55. A method according to claim 48 wherein the step of processing comprises forming a metal layer;

and wherein the anneal temperature is less than a temperature related to a characteristic of the metal layer.

56. A method according to claim 48 wherein the step of processing comprises forming an aluminum layer;

and wherein the anneal temperature is less than about 450°

C.

57. A method according to claim 48 wherein the step of processing comprises forming an aluminum layer, and forming a barrier metal between the aluminum layer and substrate;

and wherein the anneal temperature is in a range of about 450 to 550°

C.

58. A method according to claim 48 wherein the step of processing comprises forming at least doped region;

further comprising the step of forming at least one metal layer after the annealing step; and

wherein the anneal temperature is less than about 800°

C.

59. A method according to claim 48 wherein the anneal temperature is greater than about 400°

C.

60. A method according to claim 48 wherein the step of processing comprises completely processing the at least one substrate to form all active devices and interconnections.

61. A method according to claim 48 wherein the at least one active device comprises at least one MOSFET control device.

63. A method according to claim 61 further comprising the step of thinning at least one of the substrates prior to the bonding step.

64. A method according to claim 61 wherein the step of forming an epitaxial layer comprises forming an epitaxial doped layer to define a relatively thin buffer layer.

65. A method according to claim 64 wherein the step of forming the doped epitaxial layer comprises forming same to have a dopant concentration greater than an adjacent substrate portion.

62. A method for making a semiconductor circuit from a plurality of semiconductor substrates, the method comprising the steps of:

processing at least one surface of at least one of the substrates to form at least one active device of the semiconductor circuit;

forming an epitaxial layer on a surface of at least one substrate opposite the processed surface;

bonding the plurality of substrates together after the processing and thinning steps so that the at least one processed surface including the at least one active device defines an outer surface of the semiconductor circuit; and

annealing the bonded together substrates at an anneal temperature so as to not adversely effect the at least one active device.

66. A method according to claim 62 wherein the at least one substrate comprises silicon and the epitaxial layer comprises germanium.

67. A method according to claim 62 wherein the step of processing comprises forming a metal layer;

and wherein the anneal temperature is less than a temperature related to a characteristic of the metal layer.

68. A method according to claim 62 wherein the step of processing comprises forming an aluminum layer;

and wherein the anneal temperature is less than about 450°

C.

69. A method according to claim 62 wherein the step of processing comprises forming an aluminum layer, and forming a barrier metal between the aluminum layer and substrate;

and wherein the anneal temperature is in a range of about 450 to 550°

C.

70. A method according to claim 62 wherein the step of processing comprises forming at least doped region;

further comprising the step of forming at least one metal layer after the annealing step; and

wherein the anneal temperature is less than about 800°

C.

71. A method according to claim 62 wherein the anneal temperature is greater than about 400°

C.

72. A method according to claim 62 wherein the step of processing comprises completely processing the at least one substrate to form all active devices and interconnections.

73. A method according to claim 62 wherein the at least one active device comprises at least one MOSFET control device.

79. A method according to claim 62 wherein the step of processing comprises forming an aluminum layer, and forming a barrier metal between the aluminum layer and substrate;

and wherein the anneal temperature is in a range of about 450 to 550°

C.

74. A method for making a semiconductor circuit from a plurality of semiconductor substrates, the method comprising the steps of:

processing at least one surface of at least one of the substrates to form at least one active device of the semiconductor circuit;

implanting a region of at least one substrate opposite the processed surface in a predetermined pattern to define a plurality of laterally spaced lifetime killing implant regions;

bonding the plurality of substrates together after the processing and thinning steps so that the at least one processed surface including the at least one active device defines an outer surface of the semiconductor circuit; and

annealing the bonded together substrates at an anneal temperature so as to not adversely effect the at least one active device and the implanted regions.

75. A method according to claim 74 further comprising the step of thinning at least one of the substrates prior to the bonding step.

76. A method according to claim 75 wherein the lifetime killing implant comprises at least one of protons, helium, carbon, oxygen, argon, silicon, platinum, palladium, gold, iron and nickel.

77. A method according to claim 74 wherein the step of processing comprises forming a metal layer;

and wherein the anneal temperature is less than a temperature related to a characteristic of the metal layer.

78. A method according to claim 74 wherein the step of processing comprises forming an aluminum layer;

and wherein the anneal temperature is less than about 450°

C.

80. A method according to claim 74 wherein the step of processing comprises forming at least doped region;

further comprising the step of forming at least one metal layer after the annealing step; and

wherein the anneal temperature is less than about 800°

C.

81. A method according to claim 74 wherein the anneal temperature is greater than about 400°

C.

82. A method according to claim 74 wherein the step of processing comprises completely processing the at least one substrate to form all active devices and interconnections.

83. A method according to claim 74 wherein the at least one active device comprises at least one MOSFET control device.