Multi-layer circuit having a via matrix interlayer connection and method for fabricating the same

• US 6,153,508 A
• Filed: 02/19/1998
• Issued: 11/28/2000
• Est. Priority Date: 06/14/1996
• Status: Expired due to Fees

• Current Assignee: 3M Innovative Properties Company (3M Company)
• Original Assignee: 3M Innovative Properties Company (3M Company)
• Inventors: Harvey, Paul Marlan
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Davis, Jamie L.
• Application Number:
  US09/026,090
• Time in Patent Office: 1,013 Days
• Field of Search: 438/622, 438/108, 438/629, 438/637, 438/642
• US Class Current: 438/622
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/09781 Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• CPC Class Codes: H05K 2201/0979 Redundant conductors or connections, i.e. more than one current path between two points
• CPC Class Codes: H05K 3/42 Plated through-holes or plated via connections

Abstract

An interlayer connection for electrically connecting first and second conductive elements and reducing interlayer registration requirements is disclosed. The interlayer connection includes a first layer including a first electrically conductive element, a second layer including a second electrically conductive element, and a third layer disposed between the first layer and the second layer. The third layer includes an electrically insulative portion having a matrix of immediately adjacent vias therethrough. A selected plurality of immediately adjacent vias within the matrix are disposed between the first and the second electrically conductive elements and contain electrically conductive material forming a conductive path between the first and the second electrically conductive elements.

Claims

1. A method of fabricating a circuit on a substrate, comprising:

forming a matrix of immediately adjacent vias through a flexible electrically insulative substrate;

filling a selected plurality of immediately adjacent vias within said matrix with an electrically conductive material; and

forming a first electrically conductive element on a top surface of said substrate and a second electrically conductive element on a bottom surface of said substrate, wherein said selected plurality of immediately adjacent vias are disposed between said first and said second electrically conductive elements such that a conductive path between said first and said second electrically conductive elements is established.

2. The method of fabricating a circuit of claim 1, wherein a particular dimension of said second electrically conductive element has a selected width, and wherein a width of said matrix along said particular dimension of said second electrically conductive element is less than said selected width.

3. The method of fabricating a circuit of claim 1, wherein a particular dimension of said second electrically conductive element has a selected width, and wherein a width of said matrix along said particular dimension of said second electrically conductive element is greater than said selected width.

4. The method of fabricating a circuit of claim 1, wherein said step of forming a matrix of immediately adjacent vias through said substrate comprises laser drilling said matrix of immediately adjacent vias through said substrate.

5. The method of fabricating a circuit of claim 1, wherein said step of forming a matrix of immediately adjacent vias through said substrate is performed prior to said step of forming said first and said second electrically conductive elements.

6. The method of fabricating a circuit of claim 1, wherein said step of filling said selected plurality of immediately adjacent vias comprises plating said selected plurality of immediately adjacent vias with a selected metal.

7. The method of fabricating a circuit of claim 1, and further comprising:

following said step of forming said first and said second electrically conductive elements, etching each via within said matrix that is not within said selected plurality of immediately adjacent vias.

8. The method of fabricating a circuit of claim 1, and further comprising:

prior to said step of forming said first and said second electrically conductive elements, defining said at least one of said first and said second electrically conductive elements utilizing photolithography.