High density plasma passivation layer and method of application

• US 6,153,543 A
• Filed: 08/09/1999
• Issued: 11/28/2000
• Est. Priority Date: 08/09/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Chesire, Daniel P., Martin, Edward P. Jr., Kotzias, Barbara D., Barba, Rafael N., Olmer, Leonard J.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Ghyka, Alexander G.
• Application Number:
  US09/370,422
• Time in Patent Office: 477 Days
• Field of Search: 438/763, 438/787, 438/791, 438/624
• US Class Current: 438/791
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A method of forming a passivation layer over features located on a top layer on a semiconductor device comprises depositing a first void-free layer of a dielectric over the top layer using high density plasma chemical vapor deposition. A second void-free layer can additionally be deposited over the first void-free layer. The first void-free layer can be formed from a silicon oxide, and the second void-free layer can be formed from a silicon nitride. The first void-free layer has a top surface that is disposed at a height higher than the features. The first void-free layer can be applied in two steps. First, the void-free layer is deposited at a D/S ratio between 3.0 and 4.0 to a depth of at least 40% of the feature'"'"'s height, and then deposited at a D/S ratio of between 6.0 and 7.0.

Claims

1. A method of forming a passivation layer over features located on a top layer of a semiconductor device, comprising the steps of:

depositing a first void-free layer of a first dielectric over said top layer using high density plasma chemical vapor deposition at a first D/S ratio, and

depositing a second void-free layer of a second dielectric over said first void-free layer at a second D/S ratio, wherein said second D/S ratio is greater than said first D/S ratio.

2. The method according to claim 1, wherein said dielectrics are at least one selected from the group consisting of silicon dioxide and silicon nitride.

3. The method according to claim 1, wherein said first D/S ratio is between approximately 3.0 and 4.0 and the second D/S ratio is between approximately 6.0 and 7.0.

4. The method according to claim 1, wherein the sum of thickness of said void free first and second layers is between approximately 8000 Å

to 12000 Å

.

5. The method according to claim 1, wherein said first layer is applied with a thickness of at least 40% of the height of said features.

6. The method according to claim 1, further comprising the step of depositing a third void-free layer over said second void-free layer.

7. The method according to claim 6, wherein said third void-free layer is a nitride.

8. The method according to claim 7, wherein said nitride is silicon nitride.

9. The method according to claim 6, wherein the sum of said first void-free layer thickness and second void free layer thickness is between approximately 8000 Å

to 12000 Å and

said third void-free layer has a thickness of between approximately 2600 Å

to 3400 Å

.