Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch
First Claim
1. A configurable logic block (CLB) array for a programmable logic device, the CLB array having a plurality of CLBs arranged in a row-column configuration, wherein each CLB comprises:
- an array of configurable logic cells having a first column of configurable logic cells and a second column of configurable logic cells;
a first carry chain extending through the first column of configurable logic cells;
a second carry chain extending through the second column of configurable logic cells;
a carry initialization circuit coupled to the first column of configurable logic cells; and
a carry output circuit coupled to the second column of configurable logic cells, wherein each of the CLBs have identical first columns of configurable logic cells and identical second columns of configurable logic cells.
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Abstract
A carry logic circuit is provided for an array of configurable logic blocks (CLBs), wherein each configurable logic block includes an array of logic cells arranged in rows and columns. At least one column of logic cells includes a carry output signal selection circuit. At least one other column of logic cells includes a carry initialization circuit. The locations of the carry output signal selection circuits and carry initialization circuits are identical in each of the CLBs, and the CLBs have identical first columns of configurable logic cells and identical second columns of configurable logic cells. Dedicated routing circuitry is provided for column shifting the carry chains between vertically adjacent CLBs. Column shifting is performed such that a column of logic cells in one CLB is coupled to a non-corresponding column of logic cells in a vertically adjacent CLB. For example, the routing circuitry may perform column shifting such that a first column of logic cells in a first CLB is connected to a second column of logic cells in a vertically adjacent second CLB. Also described are methods for performing a carry logic function in an FPGA.
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Citations
9 Claims
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1. A configurable logic block (CLB) array for a programmable logic device, the CLB array having a plurality of CLBs arranged in a row-column configuration, wherein each CLB comprises:
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an array of configurable logic cells having a first column of configurable logic cells and a second column of configurable logic cells; a first carry chain extending through the first column of configurable logic cells; a second carry chain extending through the second column of configurable logic cells; a carry initialization circuit coupled to the first column of configurable logic cells; and a carry output circuit coupled to the second column of configurable logic cells, wherein each of the CLBs have identical first columns of configurable logic cells and identical second columns of configurable logic cells. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of implementing a carry chain using an array of identical configurable logic blocks (CLBs), the method comprising the steps of:
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initializing a carry input chain in a first slice of a first CLB; generating a first set of carry signals in the first slice of the first CLB; routing the first set of carry signals to a second slice of a vertically adjacent second CLB, wherein the second slice of the second CLB is offset from the first slice of the first CLB along a horizontal axis. - View Dependent Claims (9)
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Specification