Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch

• US 6,154,053 A
• Filed: 04/20/1999
• Issued: 11/28/2000
• Est. Priority Date: 09/02/1993
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: New, Bernard J.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/295,735
• Time in Patent Office: 588 Days
• Field of Search: 326/41, 326/40, 326/39, 326/38, 326/37, 708/711, 708/707, 708/703
• US Class Current: 326/41
• CPC Class Codes: G06F 2207/4812 Multiplexers
• CPC Class Codes: G06F 7/503 using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
• CPC Class Codes: G06F 7/507 using selection between two conditionally calculated carry or sum values
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A carry logic circuit is provided for an array of configurable logic blocks (CLBs), wherein each configurable logic block includes an array of logic cells arranged in rows and columns. At least one column of logic cells includes a carry output signal selection circuit. At least one other column of logic cells includes a carry initialization circuit. The locations of the carry output signal selection circuits and carry initialization circuits are identical in each of the CLBs, and the CLBs have identical first columns of configurable logic cells and identical second columns of configurable logic cells. Dedicated routing circuitry is provided for column shifting the carry chains between vertically adjacent CLBs. Column shifting is performed such that a column of logic cells in one CLB is coupled to a non-corresponding column of logic cells in a vertically adjacent CLB. For example, the routing circuitry may perform column shifting such that a first column of logic cells in a first CLB is connected to a second column of logic cells in a vertically adjacent second CLB. Also described are methods for performing a carry logic function in an FPGA.

Claims

1. A configurable logic block (CLB) array for a programmable logic device, the CLB array having a plurality of CLBs arranged in a row-column configuration, wherein each CLB comprises:

an array of configurable logic cells having a first column of configurable logic cells and a second column of configurable logic cells;

a first carry chain extending through the first column of configurable logic cells;

a second carry chain extending through the second column of configurable logic cells;

a carry initialization circuit coupled to the first column of configurable logic cells; and

a carry output circuit coupled to the second column of configurable logic cells, wherein each of the CLBs have identical first columns of configurable logic cells and identical second columns of configurable logic cells.

2. The CLB array of claim 1, further comprising a plurality of routing circuits located between the CLBs, wherein each routing circuit comprises a first set of conductors connecting the first column of configurable logic cells each in CLB with the second column of configurable logic cells in a vertically adjacent CLB and a second set of conductors connecting the second column of configurable logic cells in each CLB with the first column of configurable logic cells in a vertically adjacent CLB.

3. The CLB array of claim 1, wherein the first carry chain and the second carry chain are dual carry chains.

4. The CLB array of claim 1, wherein each CLB further comprises:

one or more additional columns of configurable logic cells; and

a carry chain extending through each of the one or more additional columns of configurable logic cells.

5. The CLB array of claim 4, further comprising a plurality of routing circuits located between the CLBs, wherein each routing circuit comprises a first set of conductors connecting the first column of configurable logic cells in each CLB with a first one of the one or more additional columns of configurable logic cells in a vertically adjacent CLB, and a second set of conductors connecting the second column of configurable logic cells in each CLB with the first column of configurable logic cells in a vertically adjacent CLB.

6. The CLB array of claim 5, wherein each routing circuit further comprises a third set of conductors connecting the first one of the one or more additional columns of configurable logic cells to a second one of the one or more additional columns of configurable logic cells in a vertically adjacent CLB.

7. The CLB array of claim 6, wherein each routing circuit further comprises a fourth set of conductors connecting the second one of the one or more additional columns of configurable logic cells to the second column of configurable logic cells in a vertically adjacent CLB.

8. A method of implementing a carry chain using an array of identical configurable logic blocks (CLBs), the method comprising the steps of:

initializing a carry input chain in a first slice of a first CLB;

generating a first set of carry signals in the first slice of the first CLB;

routing the first set of carry signals to a second slice of a vertically adjacent second CLB, wherein the second slice of the second CLB is offset from the first slice of the first CLB along a horizontal axis.

9. The method of claim 8, further comprising the step of generating a second set of carry signals in the second slice of the second CLB, wherein the second set of carry signals are generated in response to the first set of carry signals.