Load circuit having extended reverse voltage protection

• US 6,154,081 A
• Filed: 06/15/1999
• Issued: 11/28/2000
• Est. Priority Date: 06/15/1999
• Status: Expired due to Term

• Current Assignee: Delphi Technologies Ip Limited (BorgWarner Incorporated)
• Original Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Inventors: Burnham, Adam L., Du Bois, Paul Louis, Crawford, Daniel Alexander, Kekel, Steven C., Pakkala, William Frank
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/333,461
• Time in Patent Office: 532 Days
• Field of Search: 327/309, 327/545, 327/546, 361/54, 361/56, 361/91.1, 361/91.5
• US Class Current: 327/309
• CPC Class Codes: H02H 11/003 using a field effect transistor as protecting element in one of the supply lines
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches

Abstract

An improved reverse voltage protection circuit that protects sensitive electronic devices from damage due to both reversed battery connections and source voltage interruptions. An N-channel protection FET is inversely connected between the negative terminal of the protected device and ground, and the conduction of the protection FET is extended during a reverse transient protection period following interruption of the source voltage. A capacitor connected across the gate-to-source circuit of the protection FET is charged from the source voltage through a low impedance charging circuit including a diode to prevent the capacitor from discharging, and is discharged during an interruption of the source voltage through a high impedance discharging circuit connected in parallel with the charging circuit.

Claims

1. A protected load circuit powered by a power source having first and second polarity terminals, comprising:

first and second load circuit terminals normally connected to the first and second terminals of said power source, respectively;

a load circuit including an electrical load, a load switching device, and a protection transistor connected in series, the electrical load being electrically coupled to the first load circuit terminal, and the protection transistor being electrically coupled to the second load circuit terminal, the protection transistor being effective in a conductive state to electrically couple said load switching device to the second load circuit terminal, and in a non-conductive state to electrically isolate the load switching device from the second load circuit terminal;

a capacitor coupled to a control terminal of said protection transistor, said capacitor being effective when charged to bias said protection transistor to said conductive state, and when discharged to bias said protection transistor to said non-conductive state;

a charging circuit for charging said capacitor to bias said protection transistor to said conductive state when the first and second load circuit terminals are connected to the first and second polarity terminal of said power source, respectively, but for allowing said capacitor to bias said protection transistor to said non-conductive state when the first and second polarity terminals of said power source are reversed; and

a discharging circuit for discharging said capacitor during a discharge interval when the voltage across said load circuit is momentarily reversed due to a disconnection of said power source, thereby allowing said protection transistor to remain in said conductive state during said discharge interval for protecting said load switching device from damage due to the momentary voltage reversal.

2. The protected load circuit of claim 1, wherein said protection transistor is a FET having a source terminal connected to said load switching device and said capacitor is connected between said control terminal and said source terminal.

3. The protected load circuit of claim 2, wherein said charging circuit comprises a first resistor and diode connected in series between said first load circuit terminal and said control terminal.

4. The protected load circuit of claim 3, wherein said discharging circuit comprises a second resistor connected in parallel with said charging circuit.

5. The protected load circuit of claim 2, wherein said discharging circuit includes a resistor connected between said first load circuit terminal and said control terminal.

6. The protected load circuit of claim 1, wherein said discharge interval is at least as long in duration as an expected duration of said momentary voltage reversal.

7. The protected load circuit of claim 1, wherein:

said protection transistor is a FET having a source terminal connected to said load switching device and said capacitor is connected between said control terminal and said source terminal;

said charging circuit comprises a first resistor and diode connected in series between said first load circuit terminal and said control terminal;

said discharging circuit comprises a second resistor connected in parallel with said charging circuit; and

said discharge interval is at least as long in duration as an expected duration of said momentary voltage reversal.

8. The protected load circuit of claim 7, wherein said load switching device is a FET having a source terminal connected to said protection transistor and a gate terminal referenced to said second load circuit terminal, the protection transistor operating during said discharge interval to maintain said source terminal at substantially the same potential as said gate terminal, thereby protecting said FET by limiting a potential difference between said gate and source terminals during said discharge interval.