System and method of controlling access to privilege partitioned address space for a model specific register file
First Claim
1. A processor including an address space, the processor comprising:
- one or more registers wherein each of said one or more registers is assigned to one of a plurality of access regions and each of said plurality of access regions is assigned a privilege level;
a validity check circuit configured to receive an address of a first register of said one or more registers, wherein said validity check circuit is configured to permit access to said first register if a privilege level input correlates to the privilege level assigned to the access region of that first register; and
wherein said one or more registers are model specific registers.
3 Assignments
0 Petitions
Accused Products
Abstract
A system and method for controlling access to privilege partitioned address space for a model specific register file. A superscalar microprocessor includes a plurality of model specific registers (MSRs). MSRs differ between various implementations of a microprocessor architecture. The MSRs are allocated to access regions within a MSR file. Each access region of the MSR file is assigned access attributes. The MSRs are allocated such that the access region and the access attributes of the MSRs are defined by the address of the MSRs. Access to the MSRs is controlled by comparing the address of the MSR to the current privilege level of the microprocessor. In one embodiment, a validity check circuit is used to control access to the MSRs. If an access is attempted to a MSR that cannot be accessed at the current microprocessor privilege level, access to the register is denied and an exception is generated. In one embodiment, an address checker may be used to verify whether a MSR address is within a valid range. The MSR file may be divided into regions, with access granted based on a microprocessor being in a supervisory mode or a user mode.
82 Citations
32 Claims
-
1. A processor including an address space, the processor comprising:
-
one or more registers wherein each of said one or more registers is assigned to one of a plurality of access regions and each of said plurality of access regions is assigned a privilege level; a validity check circuit configured to receive an address of a first register of said one or more registers, wherein said validity check circuit is configured to permit access to said first register if a privilege level input correlates to the privilege level assigned to the access region of that first register; and wherein said one or more registers are model specific registers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A method of controlling access to registers in an address space of a computer system, the method comprising:
-
allocating registers to access regions of said address space, wherein each of said access regions is assigned a privilege level, and wherein said registers are model specific registers; receiving a privilege level input; receiving an address of a register, wherein said address identifies an access region to which said register is allocated; comparing said privilege level assigned to said access region identified by said address of said register to said privilege level input; and accessing said register if said privilege level assigned to said access region identified by said address of said register correlates to said privilege level input, wherein said register is a model specific register. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. A computer system comprising:
-
a microprocessor wherein said microprocessor includes; one or more registers wherein each of said one or more registers is assigned to one of a plurality of access regions and each of said plurality of access regions is assigned a privilege level; a validity check circuit configured to receive an address of a first register of said one or more registers, wherein said validity check circuit is configured to permit access to said first register if a privilege level input correlates to the privilege level assigned to the access region of that first register, wherein said registers are model specific registers; a bus bridge coupled to said microprocessor; a main memory coupled to said microprocessor; and an input/output device coupled to said bus bridge. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
-
Specification