Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain

• US 6,154,821 A
• Filed: 03/10/1998
• Issued: 11/28/2000
• Est. Priority Date: 03/10/1998
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Bystrom, Todd W., Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A., Davis, Paul G., May, Bradley A.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): KIM, HONG CHONG
• Application Number:
  US09/038,358
• Time in Patent Office: 994 Days
• Field of Search: 711/170, 711/167, 711/105, 711/154, 711/156, 365/194, 365/233, 713/401, 713/400, 713/503, 713/500, 713/501, 713/600
• US Class Current: 711/170
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

Claims

1. A method for initializing a plurality of dynamic random access memory (DRAM) devices coupled to at least one memory controller, the method comprising the step of levelizing a read domain of at least one of the plurality of DRAM devices, wherein the step of levelizing comprises configuring each of the plurality of DRAM devices to respond to read commands from the at least one memory controller within a same number of clock cycles, wherein the plurality of DRAM devices do not each operate at the same speed.

2. The method of claim 1, wherein configuring each of the plurality of DRAM devices comprises:

determining the response time of each of the plurality of DRAM devices using information communicated over at least one bus;

determining the longest response time of the response times;

computing a delay for each of the plurality of DRAM devices; and

programming the delay in each of the plurality of DRAM devices by writing values to at least one register of each of the plurality of DRAM devices.

3. The method of claim 2, wherein the computed delay results in the response time of each of the plurality of DRAM devices equaling the longest response time.

4. The method of claim 2, wherein the delay is programmed using a serial chain coupled between each of the plurality of DRAM devices.

5. The method of claim 2, wherein the step of determining the response time comprises the steps of:

writing at least one logic one to at least one memory location of a DRAM device;

issuing a read command to the at least one memory location of the DRAM device; and

measuring a response time between the issuance of the read command and the receipt of the at least one logic one from the at least one memory location of the DRAM device.

6. The method of claim 2, wherein the step of programming the delay comprises writing delay values to each of two registers in each of the plurality of DRAM devices.

7. The method of claim 1, further comprising the steps of:

determining a first minimum clock cycle offset between a read command and a subsequent write command communicated to the plurality of DRAM devices using the at least one bus; and

determining a second minimum clock cycle offset between a write command and a subsequent read command communicated to the plurality of DRAM devices using the at least one bus; and

configuring the at least one memory controller to use the first and the second minimum clock cycle offsets.

8. The method of claim 1, wherein the plurality of DRAM devices are coupled to at least one bus, wherein a propagation delay from the at least one memory controller to at least one of the plurality of DRAM devices exceeds one clock cycle.

9. The method of claim 1, wherein the plurality of DRAM devices are operating at a first frequency, wherein at least one register of the plurality of DRAM devices is accessed at a second frequency.

10. The method of claim 9, wherein the first frequency is 400 megahertz (MHz) and the second frequency is 1 megahertz (MHz).

11. The method of claim 9, wherein the first frequency is 50 megahertz (MHz) and the second frequency is 1 megahertz (MHz).

12. The method of claim 1, wherein a first read command response time for a first DRAM device is different than second read command response time of a second DRAM device.

13. An apparatus for initializing a plurality of dynamic random access memory (DRAM) devices comprising:

at least one bus coupled among the plurality of DRAM devices and at least one memory controller;

at least one levelizing circuit configured to levelize a read domain of at least one of the plurality of DRAM devices, wherein levelizing comprises configuring each of the plurality of DRAM devices to respond to read commands from the at least one memory controller in the same amount of time.

14. The apparatus of claim 13, wherein the at least one memory controller comprises the at least one circuit configured to levelize the read domain.

15. The apparatus of claim 13, wherein the at least one levelizing circuit comprises:

timing circuitry configured to determine the response time of each of the plurality of DRAM devices using information communicated over the at least one bus;

evaluation circuitry configured to determine the longest response time of the response times;

delay circuitry configured to compute a delay for each of the plurality of DRAM devices so that the response time of each of the plurality of DRAM devices equals the longest response time; and

programming circuitry configured to program the delay in each of the plurality of DRAM devices by writing values to at least one register of each of the plurality of DRAM devices using a serial link coupled among the plurality of DRAM devices and the at least one memory controller.

16. The apparatus of claim 13, further comprising:

a first offset circuit configured to determine a minimum clock cycle offset between a read command and a subsequent write command communicated to the plurality of DRAM devices over the at least one bus; and

a second offset circuit configured to determine a minimum clock cycle offset between a write command and a subsequent read command communicated to the plurality of DRAM devices over the at least one bus.

17. The apparatus of claim 13, further comprising delay lock loop (DLL) configuration circuitry configured to configure at least one power-down exit register for DLL acquisition.

18. The apparatus of claim 13, wherein 32 DRAM devices are coupled to the at least one bus and the at least one memory controller.

19. The apparatus of claim 13, wherein the at least one bus is 8-bits wide, wherein the at least one bus is logically divided into primary control packets and secondary control packets.

20. A computer readable medium containing executable instructions which, when executed in a processing system, causes the system to perform the steps for initializing a plurality of dynamic random access memory (DRAM) devices comprising levelizing a read domain of at least one of the plurality of DRAM devices, wherein the step of levelizing comprises configuring each of the plurality of DRAM devices to respond to read commands from the at least one memory controller within a same number of clock cycles, wherein the plurality of DRAM devices do not each operate at the same speed.

21. The computer readable medium of claim 20, wherein the system is configured to perform the step of levelizing by:

determining the response time of each of the plurality of DRAM devices using information communicated over at least one bus;

determining the longest response time of the response times;

computing a delay for each of the plurality of DRAM devices; and

programming the delay in each of the plurality of DRAM devices by writing values to at least one register of each of the plurality of DRAM devices.

22. The computer readable medium of claim 21, wherein the system is configured to perform the step of determining the response time by:

writing at least one logic one to at least one memory location of a DRAM device;

issuing a read command to the at least one memory location of the DRAM device; and

measuring a response time between the issuance of the read command and the receipt of the at least one logic one from the at least one memory location of the DRAM device.

23. The computer readable medium of claim 20, wherein the executable instructions further cause the system to perform the steps of:

determining a first minimum clock cycle offset between a read command and a subsequent write command communicated to the plurality of DRAM devices using the at least one bus; and

determining a second minimum clock cycle offset between a write command and a subsequent read command communicated to the plurality of DRAM devices using the at least one bus; and

configuring the at least one memory controller to use the first and the second minimum clock cycle offsets.

24. The computer readable medium of claim 20, wherein the executable instructions further cause the system to perform the step of configuring at least one power-down exit register for use in delay lock loop (DLL) acquisition using a serial chain coupled between each of the plurality of DRAM devices, wherein configuring the at least one power-down exit register comprises storing coarse biasing information of the DLL in a first register of an associated DRAM device and storing fine biasing information of the DLL in a second register of the associated DRAM device, wherein the DLL uses the biasing information from the first and the second registers upon recovery from a low-power mode.