Microprocessor
First Claim
1. A microprocessor including at least two instruction execution units for decoding and executing instruction codes read from an externally provided common instruction memory, comprising:
- a first instruction execution unit for supplying an address to said instruction memory and for decoding and executing an instruction code read from said instruction memory in accordance with said address;
an instruction cache for storing plural instruction codes read from said instruction memory;
a second instruction execution unit for supplying an address to said instruction cache and for decoding and executing an instruction code read from said instruction cache in accordance with said address; and
a cache controller for determining whether or not the instruction code specified by said address supplied from said second instruction execution unit to said instruction cache is present in said instruction cache, and when the instruction code is not present, for controlling said second instruction execution unit to suspend decoding and execution of the instruction code and controlling said first instruction execution unit to supplement an instruction block including the instruction code from said instruction memory to said instruction cache.
2 Assignments
0 Petitions
Accused Products
Abstract
On a microprocessor chip mounting a central processing unit (CPU) for controlling the entire operation of electronic equipment and a digital signal processor (DSP) for processing a specific signal in the electronic equipment, an instruction cache for temporarily storing a DSP program and a cache controller are additionally mounted, and the DSP program and a CPU program are stored in an externally provided instruction memory. The cache controller controls the DSP to wait and interrupts the CPU when a cache miss occurs. The CPU executes a predetermined interrupt processing routine so as to supplement an instruction block including the instruction code from the instruction memory to the instruction cache. Thus, an on-chip memory used for storing instruction codes to be decoded and executed by the DSP can be reduced.
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Citations
6 Claims
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1. A microprocessor including at least two instruction execution units for decoding and executing instruction codes read from an externally provided common instruction memory, comprising:
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a first instruction execution unit for supplying an address to said instruction memory and for decoding and executing an instruction code read from said instruction memory in accordance with said address; an instruction cache for storing plural instruction codes read from said instruction memory; a second instruction execution unit for supplying an address to said instruction cache and for decoding and executing an instruction code read from said instruction cache in accordance with said address; and a cache controller for determining whether or not the instruction code specified by said address supplied from said second instruction execution unit to said instruction cache is present in said instruction cache, and when the instruction code is not present, for controlling said second instruction execution unit to suspend decoding and execution of the instruction code and controlling said first instruction execution unit to supplement an instruction block including the instruction code from said instruction memory to said instruction cache. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification