Microprocessor

• US 6,154,830 A
• Filed: 11/13/1998
• Issued: 11/28/2000
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Sugimura, Toshio
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US09/190,227
• Time in Patent Office: 746 Days
• Field of Search: 711/125, 712/205, 712/35, 712/34, 712/38, 712/42, 712/43
• US Class Current: 712/205
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

On a microprocessor chip mounting a central processing unit (CPU) for controlling the entire operation of electronic equipment and a digital signal processor (DSP) for processing a specific signal in the electronic equipment, an instruction cache for temporarily storing a DSP program and a cache controller are additionally mounted, and the DSP program and a CPU program are stored in an externally provided instruction memory. The cache controller controls the DSP to wait and interrupts the CPU when a cache miss occurs. The CPU executes a predetermined interrupt processing routine so as to supplement an instruction block including the instruction code from the instruction memory to the instruction cache. Thus, an on-chip memory used for storing instruction codes to be decoded and executed by the DSP can be reduced.

Claims

1. A microprocessor including at least two instruction execution units for decoding and executing instruction codes read from an externally provided common instruction memory, comprising:

a first instruction execution unit for supplying an address to said instruction memory and for decoding and executing an instruction code read from said instruction memory in accordance with said address;

an instruction cache for storing plural instruction codes read from said instruction memory;

a second instruction execution unit for supplying an address to said instruction cache and for decoding and executing an instruction code read from said instruction cache in accordance with said address; and

a cache controller for determining whether or not the instruction code specified by said address supplied from said second instruction execution unit to said instruction cache is present in said instruction cache, and when the instruction code is not present, for controlling said second instruction execution unit to suspend decoding and execution of the instruction code and controlling said first instruction execution unit to supplement an instruction block including the instruction code from said instruction memory to said instruction cache.

2. The microprocessor of claim 1, wherein said cache controller includes:

a tag register for storing a tag consisting of a high order portion of an address specifying an instruction code present in said instruction cache; and

a comparator for determining whether or not a high order portion of said address supplied from said second instruction execution unit to said instruction cache accords with said tag stored in said tag register, and

said tag register is updated by said first instruction execution unit when the instruction block including the instruction code is supplemented from said instruction memory to said instruction cache.

3. The microprocessor of claim 1, wherein said instruction cache includes plural ports for conducting read and write of instruction codes in parallel.

4. The microprocessor of claim 1, wherein said instruction cache includes plural banks, said cache controller includes:

plural tag registers each for storing a tag consisting of a high order portion of an address specifying an instruction code present in the corresponding bank of said instruction cache; and

plural comparators respectively corresponding to said plural tag registers for determining whether or not a high order portion of said address supplied from said second instruction execution unit to said instruction cache accords with the tag stored in the corresponding tag register among said plural tag registers, and

the corresponding tag register among said plural tag registers is updated by said first instruction execution unit when the instruction block including the instruction code is supplemented from said instruction memory to one of said banks of said instruction cache.

5. The microprocessor of claim 1, wherein said cache controller has a function to control said first instruction execution unit to previously supplement a subsequent instruction block including plural subsequent instruction codes from said instruction memory to said instruction cache when a low order portion of said address supplied from said second instruction execution unit to said instruction cache is not smaller than a predetermined threshold value.

6. The microprocessor of claim 1, wherein said first instruction execution unit is a central processing unit for controlling an entire operation of electronic equipment including said microprocessor, and said second instruction execution unit is a digital signal processor for processing a specific signal in said electronic equipment.