Efficient direct replacement cell fault tolerant architecture

• US 6,154,855 A
• Filed: 08/18/1999
• Issued: 11/28/2000
• Est. Priority Date: 03/22/1994
• Status: Expired due to Term

• Current Assignee: Richard S. Norman
• Original Assignee: Hyperchip Incorporated
• Inventors: Norman, Richard S.
• Primary Examiner(s): Wright, Norman M.
• Application Number:
  US09/376,194
• Time in Patent Office: 468 Days
• Field of Search: 714/10, 714/25, 714/30, 714/29, 714/48
• US Class Current: 714/10
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G02F 1/135 Liquid crystal cells structurally associated with a photoconducting or a ferro-electric layer, the properties of which can be optically or electrically varied G02F1/133348 takes precedence
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2041 with more than one idle spare processing component
• CPC Class Codes: G06F 11/2051 in regular structures
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 3/041 Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• CPC Class Codes: G06F 3/043 using propagating acoustic waves
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 2330/10 Dealing with defective pixels
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/2088 with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
• CPC Class Codes: H01L 27/148 Charge coupled imagers individual charge coupled devices H01L29/765
• CPC Class Codes: H01L 27/14831 Area CCD imagers

Abstract

A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to by organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into single monolithic entity.

Claims

1. A complete data processing system comprising integrated circuits, with all said integrated circuits within said complete data processing system being fabricated on a single monolithic substrate, said complete data processing system including means for input directly from a source external to the system without that input signal being relayed through a physical connection between the monolithic data processing system and the source, processing means, memory means, and means for output to a receiver external to the system without that output signal being relayed through a physical connection between the monolithic data processing system and the receiver.

2. A complete data processing system as defined in claim 1, wherein the complete data processing system is lithographically fabricated on a single substrate.

3. A complete data processing system as defined in claim 1, wherein the output means include means to send human-comprehensible output directly to a human operator without that output being processed by or passing through any separately fabricated device.

4. A complete data processing system as defined in claim 3, wherein the complete data processing system is lithographically fabricated on a single substrate.

5. A complete data processing system as defined in claim 3, wherein the input means include means to receive input directly from a human operator without that input signal being relayed through or processed by any separately fabricated device.

6. A complete data processing system as defined in claim 5, wherein the complete data processing system is lithographically fabricated on a single substrate.

7. A complete data processing system as defined in claim 5, wherein the system also has power absorption and/or power storage means within the thin sheet.

8. A complete data processing system fabricated as a single thin sheet as defined in claim 6, wherein the system also has means for power absorption and/or power storage fabricated on the monolithic substrate.

9. A data processing system comprising a monolithic array of cells or a monolithic network of cells from which an array of cells can be organized, with each said array cell having direct output means to send an output signal directly to a device external to said data processing system without said output signal being relayed through other cells, through a physical carrier common to that cell and other said array cells, or through an output device fabricated as a separate physical entity from the cell array, and each said cell having processing means and memory means that are sufficient to extract a datum from a compressed data stream prior to transmitting that datum through the cell'"'"'s direct output means.

10. A complete data processing system fabricated as a thin sheet whose total thickness is less than 1 millimeter, said complete data processing system including means for input directly from a source external to the system without that input signal being relayed through a physical connection between the monolithic data processing system and the source;

and means for processing, memory, and direct output as defined in claim 9.

11. A system as defined in claim 10, wherein the direct output means include optical output means and each array cell has spare optical output elements.

12. A system as defined in claim 10, wherein each said array cell has direct input means to receive an input signal directly from a device external to the system without that input signal being relayed through another cell, through a physical carrier common to that cell and other said cells, or through an input device fabricated as a separate physical entity from the cell array.

13. A system as defined in claim 12, wherein the direct output means include optical output means and each array cell has spare optical output elements.

14. A system as defined in claim 12, wherein the direct output means include optical output means and the direct input means include means for touch detection or proximity detection.

15. A system as defined in claim 12, wherein the cells include means for individually or cooperatively focusing the cells'"'"' direct input means on an external source whose distance and/or direction are not predetermined.

16. A system as defined in claim 12, wherein the cells include means for individually or cooperatively focusing the cells'"'"' direct input means on an external source whose distance and/or direction are not predetermined.

17. A system as defined in claim 12, wherein each said array cell includes direct input means, processing means, memory means, direct output means and means for power absorption and/or power storage, all within a 1 centimeter radius of the center of the cell.

18. A system as defined in claim 10, wherein the cells include means for individually or cooperatively focusing output from the cells'"'"' direct output means on an external receiver whose distance and/or direction are not predetermined.

19. A system as defined in claim 10, wherein each said cell includes means for joining a power-sharing bus common to or associated with a plurality of cells in a region of the network of cells that is smaller than the entire network.