Glass circuit substrate and fabrication method thereof

• US 6,156,413 A
• Filed: 10/24/1997
• Issued: 12/05/2000
• Est. Priority Date: 10/25/1996
• Status: Expired due to Term

• Current Assignee: Canon Ayutthaya Limited (Canon Inc.)
• Original Assignee: Canon Ayutthaya Limited (Canon Inc.)
• Inventors: Kameyama, Makoto, Tomari, Yoshiaki, Nakai, Yasuyuki
• Primary Examiner(s): Speer, Timothy
• Assistant Examiner(s): YOUNG, BRYANT L
• Application Number:
  US08/956,700
• Time in Patent Office: 1,138 Days
• Field of Search: 428/209, 428/434, 428/469, 428/620, 428/630, 428/670-673, 428/936, 106/1.11, 106/1.24, 106/1.28
• US Class Current: 428/209
• CPC Class Codes: C23C 18/42 Coating with noble metals
• CPC Class Codes: H05K 3/181 by electroless plating adhesives therefor H05K3/387
• CPC Class Codes: Y10T 428/12528 Semiconductor component
• CPC Class Codes: Y10T 428/12597 Noncrystalline silica or noncrystalline plural-oxide component [e.g., glass, etc.]
• CPC Class Codes: Y10T 428/12875 Platinum group metal-base component
• CPC Class Codes: Y10T 428/12882 Cu-base component alternative to Ag-, Au-, or Ni-base component
• CPC Class Codes: Y10T 428/12889 Au-base component
• CPC Class Codes: Y10T 428/12896 Ag-base component
• CPC Class Codes: Y10T 428/24917 including metal layer

Abstract

A glass circuit substrate wherein nuclei of Pd (palladium) are placed on a glass substrate and a plating layer of Pd--P (palladium--phosphorus) is placed on the nuclei. A fabrication method of the glass circuit substrate comprises steps of forming nuclei of Pd on a glass substrate; and therefore forming a plating layer of Pd--P on the nuclei.

Claims

1. A glass circuit substrate comprising:

(a) a layer of palladium (Pd) nuclei on a glass substrate;

(b) a plating layer of palladium--phosphorous (Pd--P) on the layer of palladium nuclei, wherein a thickness of said Pd--P plating layer is from 0.015 μ

m to 0.500 μ

m.

2. A glass circuit substrate comprising:

(a) a layer of palladium (Pd) nuclei on a glass substrate;

(b) a plating layer of palladium-phosphorous (Pd--P) on the layer of palladium nuclei, wherein a content of phosphorus of said Pd--P plating layer is from 3.0 (wt %) to 10.0 (wt %).

3. A glass circuit substrate comprising:

(a) a layer of palladium (Pd) nuclei on a glass substrate;

(b) a plating layer of palladium-phosphorous (Pd--P) on the layer of palladium nuclei, wherein a second plating layer comprised of at least one material selected from the group consisting of Cu, Ni, Ni-P, Ag, Pd, Pd--P, Au and Pt is disposed on said Pd--P plating layer.

4. A glass circuit substrate comprising:

(a) a layer of palladium (Pd) nuclei on a glass substrate;

(b) a plating layer of palladium-phosphorous (Pd--P) on the layer of palladium nuclei, further comprising a Cu plating layer, an Ni plating layer, and an Au plating layer on said Pd--P plating layer.

5. A glass circuit substrate comprising:

(a) a layer of palladium (Pd) nuclei on a glass subsrate;

(b) a plating layer of palladium-phosphorous (Pd--P) on the layer of palladium nuclei, further comprising an Ag plating layer and an Au plating layer on said Pd--P plating layer.

6. A glass circuit substrate comprising:

(a) a layer of palladium (Pd) nuclei on a glass substrate;

(b) a plating layer of palladium-phosphorous (Pd--P) on the layer of palladium nuclei, said Pd--P plating layer having a thickness of from 0.015 μ

m to 0.500 μ

m and a phosphorous content of from 3.0 (wt%) to 10.0 (wt%); and

(c) a second plating layer comprised of at least one material selected from the group consisting of Cu, Ni, Ni-P, Ag, Pd, Pd--P, Au, and Pt disposed on said Pd--P plating layer.

7. A glass circuit substrate comprising:

(a) a layer of palladium (Pd) nuclei on a glass substrate;

(b) a plating layer of palladium-phosphorous (Pd--P) on the layer of palladium nuclei; and

(c) another Pd--P plating layer on said Pd--P plating layer, wherein said Pd--P plating layer on the layer of palladium nuclei is in an amorphous state and said another Pd--P plating layer is in a crystalline state.

9. A glass circuit substrate according to claim 7, comprising a Cu plating layer, an Ni plating layer, and an Au plating layer on said crystalline Pd--P plating layer.

10. A glass circuit substrate according to claim 7, comprising an Ag plating layer and an Au plating layer on said crystalline Pd--P plating layer.

11. A glass circuit substrate according to claim 7, comprising a Pt plating layer on said crystalline Pd--P plating layer.

12. A glass circuit substrate according to claim 7, wherein a thickness of said crystalline Pd--P layer is from 0.015 μ

m to 0.250 μ

m.

13. A glass circuit substrate according to claim 7, wherein crystallinity varies on a gradient basis at an interface between said amorphous Pd--P plating layer and said crystalline Pd--P layer.

14. A glass circuit substrate according to claim 13, having such a film structure that the P content decreases so as to be continuously gradient from said amorphous Pd--P plating layer into said crystalline Pd--P plating layer.

15. A glass circuit substrate according to claim 7, wherein a thickness of said crystalline Pd--P plating layer is from 0.015 μ

m to 0.25 μ

m.

16. A glass circuit substrate according to claim 7, wherein a content of phosphorus of said crystalline Pd--P plating layer is from 0 to 1 (wt %).

8. A glass circuit substrate comprising:

(a) a layer of palladium (Pd) nuclei on a glass substrate;

(b) a plating layer of palladium-phosphorous (Pd--P) on the layer of palladium nuclei, wherein

(c) said glass substrate is a non-roughed glass substrate and said Pd--P plating layer is an electroless plating layer; and

(d) a metal plating film is placed on said Pd--P plating layer.

17. A glass circuit substrate according to claim 8, wherein a thickness of said Pd--P film is 02. μ

m or more.

18. A glass circuit substrate according to claim 17, wherein the thickness of said Pd--P layer is 0.5 μ

m or less.

19. A glass circuit substrate according to claim 8, wherein said metal is at least one of Ag and Au.

20. A glass circuit substrate according to claim 8, comprising a mutual diffusion layer of a glass component forming said glass substrate, said Pd--P, and said metal.

21. A glass circuit substrate according to claim 8, wherein said metal film is comprised of a laminate film of a stack of plural metal layers.

22. A glass circuit substrate according to claim 20, wherein an alloy of said Pd--P and said metal is formed in said mutual diffusion layer.

23. A glass circuit substrate according to claim 20, wherein a thickness of said mutual diffusion layer is from 200 nm to 2000 nm.

24. A glass circuit substrate according to claim 8, wherein said Pd--P film comprises a pattern and said metal film also comprises a similar pattern thereto.

25. A glass circuit substrate according to claim 22, wherein an electric element is connected to said metal film.

26. A glass circuit substrate according to claim 25, wherein said electric element is selected from a wire for display of image and an IC.

27. A method for fabricating a glass circuit substrate comprising steps of:

forming nuclei of Pd (palladium) on a glass substrate; and

thereafter forming a plating layer of Pd--P (palladium-phosphorus) on said nuclei, said Pd--P plating layer having a thickness of from 0.015 μ

m to 0.500 μ

m.

28. A method for fabricating a glass circuit substrate comprising steps of:

forming nuclei of Pd (palladium) on a glass substrate; and

thereafter forming a plating layer of Pd--P (palladium-phosphorous) on said nuclei, said Pd--P plating layer having a phosphorous content of from 3.0 (wt %) to 10.0 (wt %).

29. A method for fabricating a glass circuit substrate comprising steps of:

forming nuclei of Pd (palladium) on a glass substrate; and

forming a first plating layer of Pd--P (palladium-phosphorous) on said nuclei; and

forming a second plating layer on said first plating layer;

wherein said second plating layer is comprised of a metal or an alloy of two or more selected from the group consisting of Cu, Ni, Ni--P, Ag, Pd, Pd--P, Au, and Pt.

30. A method for fabricating a glass circuit substrate comprising steps of:

forming nuclei of Pd (palladium) on a glass substrate; and

thereafter forming a plating layer of Pd--P (palladium-phosphorus) on said nuclei, said Pd--P plating layer having a thickness of from 0.015 μ

m to 0.500 μ

m and a phosphorous content of from 3.0 (wt%) to 10.0 (wt %).

33. A method for fabricating a glass circuit substrate according to claim 30, comprising a step of providing a Cu plating layer, an Ni plating layer, and an Au plating layer on said Pd--P plating layer.

34. A method for fabricating a glass circuit substrate according to claim 30, comprising a step of providing an Ag plating layer and an Au plating layer on said Pd--P plating layer.

35. A method for fabricating a glass circuit substrate according to claim 30, further comprising a step of providing another Pd--P plating layer on said Pd--P plating layer.

36. A method for fabricating a glass circuit substrate according to claim 35, wherein said Pd--P plating layer placed on said nuclei is in an amorphous state and said another Pd--P plating layer placed on the amorphous Pd--P plating layer is in a crystalline state.

37. A method for fabricating a glass circuit substrate according to claim 36, comprising a step of providing a Cu plating layer, an Ni plating layer, and an Au plating layer on said crystalline Pd--P plating layer.

38. A method for fabricating a glass circuit substrate according to claim 36, comprising a step of providing an Ag plating layer and an Au plating layer on said crystalline Pd--P plating layer.

39. A method for fabricating a glass circuit substrate according to claim 36, comprising a step of providing a Pt plating layer on said crystalline Pd--P plating layer.

40. A method for fabricating a glass circuit substrate according to claim 36, wherein a thickness of said crystalline Pd--P layer is from 0.015 μ

m to 0.250 μ

m.

31. A method for fabricating a glass circuit substrate comprising steps of:

forming nuclei of Pd (palladium) on a glass substrate;

thereafter forming a plating layer of Pd--P (palladium-phosphorus) on said nuclei; and

providing a Cu plating layer, a Ni plating layer, a Au plating layer, a Ag and a Au plating layer, and another Pt plating layer on said Pd--P plating layer.

32. A method for fabricating a glass circuit substrate comprising steps of:

forming nuclei of Pd (palladium) on a glass substrate, wherein said glass substrate is a non-roughed glass substrate;

thereafter forming a plating layer of Pd--P (palladium-phosphorus) on said nuclei wherein said Pd--P plating layer is an electroless plating layer; and

placing a metal plating film on said Pd--P plating layer.

41. A method for fabricating a glass circuit substrate according to claim 32, wherein a thickness of said Pd--P film is 0.2 μ

m or more.

42. A method for fabricating a glass circuit substrate according to claim 41, wherein the thickness of said Pd--P film is 0.5 μ

m or less.

43. A method for fabricating a glass circuit substrate according to claim 32, wherein said metal is at least one of Ag and Au.

44. A method for fabricating a glass circuit substrate according to claim 32, wherein said Pd--P film comprises a pattern and said metal film also comprises a similar pattern thereto.

45. A method for fabricating a glass circuit substrate according to claim 44, comprising a step of connecting an electric element to said metal film.