GaN-based devices using (Ga, AL, In)N base layers

• US 6,156,581 A
• Filed: 12/03/1997
• Issued: 12/05/2000
• Est. Priority Date: 01/27/1994
• Status: Expired due to Term

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: Advanced Technology Materials, Inc. (Entegris Incorporated)
• Inventors: Vaudo, Robert P., Redwing, Joan M., Tischler, Michael A., Brown, Duncan W.
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US08/984,473
• Time in Patent Office: 1,098 Days
• Field of Search: 438/46, 438/22, 438/48, 438/93, 438/479, 438/483, 438/518, 438/718, 438/931, 438/977, 438/930, 117/952, 117/953, 427/248.1, 427/255.1
• US Class Current: 438/22
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: C30B 23/02 Epitaxial-layer growth
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 25/18 characterised by the substrate
• CPC Class Codes: C30B 29/36 Carbides
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: C30B 33/00 After-treatment of single crystals or homogeneous polycrystalline material with defined structure C30B31/00 takes precedence
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02581 : Transition metal or rare earth elements
• CPC Class Codes: H01L 21/0262 : Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02664 : Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 33/007 : comprising nitride compounds
• CPC Class Codes: H01L 33/0075 : comprising nitride compounds
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: Y10S 117/915 : Separating from substrate
• CPC Class Codes: Y10T 428/13 : Hollow or container type article [e.g., tube, vase, etc.]
• CPC Class Codes: Y10T 428/21 : Circular sheet or circular blank

Abstract

A method of forming a (gallium, aluminum, indium) nitride base layer on a substrate for subsequent fabrication, e.g., by MOCVD or MBE, of a microelectronic device structure thereon. Vapor-phase (Ga, Al, In) chloride is reacted with a vapor-phase nitrogenous compound in the presence of the substrate, to form (Ga, Al, In) nitride. The (Ga, Al, In) nitride base layer is grown on the substrate by HVPE, to yield a microelectronic device base comprising a substrate with the (Ga, Al, In) nitride base layer thereon. The product of such HVPE process comprises a device quality, single crystal crack-free base layer of (Ga, Al, In) N on the substrate, in which the thickness of the base layer may, for example, be on the order of 2 microns and greater and the defect density of the base layer may, for example, be on the order of 1E8 cm^-2 or lower. Microelectronic devices thereby may be formed on the base layer, over a substrate of a foreign (poor lattice match) material, such as sapphire. Devices which may be fabricated utilizing the HVPE base layer of the invention include light emitting diodes, detectors, transistors, and semiconductor lasers.

Claims

1. A method of forming a base structure for fabrication of a microelectronic device structure thereon, comprising reacting a vapor-phase (Ga, Al, In) composition with a vapor-phase nitrogenous compound in the presence of a substrate, to grow a (Ga, Al, In) nitride base layer on the substrate, thereby yielding a microelectronic device foundation comprising the substrate with the (Ga, Al, In) nitride base layer thereon.

2. A method according to claim 1, wherein the vapor-phase (Ga, Al, In) composition comprises (Ga, Al, In) chloride or (Ga, Al, In) bromide.

3. A method according to claim 1, wherein the base layer of (Ga, Al, In) nitride comprises a single-crystal, crack-free base layer of (Ga, Al, In) nitride.

4. A method according to claim 1, wherein the base layer of (Ga, Al, In) nitride has a defect density not greater than about 1E8 defects/cm².

5. A method according to claim 1, wherein the base layer of (Ga, Al, In) nitride has a defect density not greater than about 1E7 defects/cm² .

6. A method according to claim 1, wherein the thickness of the base layer is at least about 2 microns.

7. A method according to claim 1, wherein the base layer is formed of a material selected from the group consisting of GaN, AlN, and InN.

8. A method according to claim 1, wherein the base layer is formed of a material selected from the group consisting of GaAlN, GaInN, and AlInN.

9. A method according to claim 1, wherein the base layer is formed of a material comprising GaAlInN.

10. A method according to claim 1, wherein the base layer is formed of a material comprising GaN.

11. A method according to claim 1, wherein the base layer is formed of a material comprising AlN.

12. A method according to claim 1, wherein the base layer is formed of a material comprising InN.

13. A method according to claim 1;

wherein the substrate comprises a single crystal material.

14. A method according to claim 1, wherein the substrate comprises a polycrystalline material.

15. A method according to claim 1, wherein the substrate comprises a material that is matched in thermal coefficient of expansion to the base layer of (Ga, Al, In) nitride.

16. A method according to claim 1, wherein the substrate is formed of a material selected from the group consisting of sapphire, silicon, silicon carbide, diamond, lithium gallate, lithium aluminate, ScAlMgO₄, zinc oxide, spinel, magnesium oxide, gallium arsenide, glass, silicon-on-insulator, carbonized silicon-on-insulator, carbonized silicon-on-silicon and gallium nitride.

17. A method according to claim 1, wherein the substrate comprises sapphire.

18. A method according to claim 1, wherein the substrate comprises graphite and aluminum nitride.

19. A method according to claim 1, further comprising removing the substrate from the base layer.

20. A method according to claim 19, wherein the substrate is removed from base layer by chemical and/or mechanical process.

21. A method according to claim 1, wherein the substrate is selected from the group consisting of conductive substrates, insulating substrates, semi-insulating substrates, twist-bonded substrates, compliant substrates, and patterned substrates.

22. A method according to claim 1, wherein the layer of single crystal (Ga, Al, In)N is deposited directly on the surface of the substrate.

23. A method according to claim 1, wherein the layer of single crystal (Ga, Al, In)N is deposited on an uppermost surface of one or more intermediate layers which in turn are provided on the substrate.

24. A method according to claim 1, wherein an intermediate layer is provided between the substrate and the base layer, and the intermediate layer comprises a material other than ZnO.

25. A method according to claim 1, wherein an intermediate layer is provided between the substrate and the base layer, and the intermediate layer comprises a material selected from the group consisting of SiC, (Ga, Al, In)N, and alloys of ZnO, SiC and (Ga, Al, In)N.

26. A method according to claim 1, wherein an intermediate layer is provided between the substrate and the base layer, and the intermediate layer comprises a material selected from the group consisting of SiC, (Ga, Al, In)N, and alloys of SiC and (Ga, Al, In)N.

27. A method according to claim 1, wherein the substrate is formed of a material selected from the group consisting of sapphire, silicon, and silicon carbide.

28. A method according to claim 1, wherein the substrate is selected from the group consisting of conductive substrates, insulating substrates, and semi-insulating substrates.

29. A method according to claim 1, wherein the layer of single crystal (Ga, Al, In)N is deposited directly on the surface of the substrate.

30. A method according to claim 1, wherein the layer of single crystal (Ga, Al, In)N is deposited on an uppermost surface of one or more intermediate layers which in turn are provided on the crystalline substrate.

31. A method according to claims 30, wherein the one or more intermediate layers is comprised of a material selected from the group consisting of ZnO, SiC, (Ga, Al, In)N, and alloys of SiC and (Ga, Al, In)N.

32. A method according to claim 30, wherein the one or more intermediate layers is comprised of a material selected from the group consisting of SiC, (Ga, Al, In)N, and alloys of SiC and (Ga, Al, In)N.

33. A method according to claim 30, wherein the one or more intermediate layers is comprised of a material other than ZnO.

34. A method according to claim 30, wherein the one or more intermediate layers comprise a protective layer provided thereon prior to growth of the (Ga, Al, In)N base layer, so that the protective layer prevents decomposition of the substrate while (Ga, Al, In)N base layer growth is proceeding.

35. A method according to claim 30, wherein the one or more intermediate layers modify the electrical properties of the (Ga, Al, In)N base structure, as compared to a corresponding structure lacking such intermediate layers.

36. A method according to claim 35, wherein the one or more intermediate layers increase the conductivity of the (Ga, Al, In)N base structure, as compared to a corresponding structure lacking such intermediate layers.

37. A method according to claim 35, wherein the one or more intermediate layers decrease the conductivity of the (Ga, Al, In)N base structure, as compared to a corresponding structure lacking such intermediate layers.

38. A method according to claim 1, wherein the thickness of the base layer is from about 0.5 microns to about 1000 microns.

39. A method according to claim 1, wherein the thickness of the base layer is from about 2 microns to about 25 microns.

40. A method according to claim 1, wherein the thickness of the base layer is from about 5 microns to about 20 microns.

41. A method according to claim 1, having a light emitting diode fabricated thereon, said light emitting diode having a FWHM electroluminescence spectrum peak, below threshold current, of less than 15 nm.

42. A method according to claim 41, wherein the light emitting diode comprises an InGaN light emitting diode structure base layer.

43. A method according to claim 1, further comprising forming an epitaxial layer on the base structure wherein the epitaxial layer has a V-defect density less than 1E9.

44. A method according to claim 1, further comprising forming an epitaxial layer on the base structure wherein the epitaxal layer has a V-defect density less than 1E8.

45. A method according to claim 1, further comprising forming an epitaxial layer on the base structure wherein the epitaxial layer has a V-defect density less than 1E7.

46. A method according to claim 1, wherein the base layer is greater than 100 micrometers in thickness and has a defect density, measured on sapphire as a reference material, that is less than about 1E7 defects/cm² at the upper surface of the material.

47. A method according to claim 1, wherein the nitrogenous compound is selected from the group consisting of ammonia, hydrazine, amines, and polyamine.

48. A method according to claim 1, wherein said vapor-phase (Ga, Al, In) composition comprises Ga chloride.

49. A method according to claim 48, wherein the Ga chloride is formed by contacting vapor-phase hydrogen chloride with molten gallium to yield the vapor-phase Ga chloride.

50. A method according to claim 48, wherein the base layer is grown at a growth rate of at least 10 μ

m/hour.

51. A method according to claim 48, wherein the base layer is grown at a growth rate of at least 50 μ

m/hour.

52. A method according to claim 48, wherein the base layer is grown to produce a single-crystal, substantially crack-free base layer characterized by an upper surface region with a defect density of less than 10⁸ defects/cm³.

53. A method according to claim 48, wherein the base layer is grown to produce a single-crystal, substantially crack-free base layer characterized by an upper surface region with a defect density of less than 10⁷ defects/cm³.

54. A method according to claim 48, wherein the base layer comprises GaN and the growth temperature is from about 900 to about 1200°

C.

55. A method according to claim 48, wherein the base layer comprises InN and the growth temperature is from about 650 to about 1000°

C.

56. A method according to claim 48, wherein the base layer comprises AlN and the growth temperature is from about 900 to about 1400°

C.

57. A method according to claim 48, wherein the base layer comprises GaN and the growth temperature is about 1050°

C.

58. A method according to claim 48, wherein the base layer comprises GaN and the growth temperature is about 1000°

C.

59. A method for fabrication of a microelectronic device, comprising reacting vapor-phase (Ga, Al, In) chloride with a vapor-phase nitrogenous compound in the presence of a substrate, to grow a (Ga, Al, In) nitride base layer on the substrate, thereby yielding a microelectronic device foundation comprising the substrate with the (Ga, Al, In) nitride base layer thereon, and subsequently forming a microelectronic device on the base layer.

60. A method according to claim 59, wherein the microelectronic device is formed on the base layer by a process including deposition of device layers by a deposition technique selected from the group consisting of metalorganic chemical vapor deposition (MOCVD) and molecular-beam epitaxy (MBE).

61. A method according to claim 59, wherein the microelectronic device is formed on the base layer by a process including at least one process step selected from the group consisting of ion implantation and etching.

62. A method according to claim 59, wherein the microelectronic device is selected from the group consisting of light emitting diodes, detectors, filters, transistors, rectification circuitry, and semiconductor lasers.