Method of forming a trench capacitor using a rutile dielectric material

• US 6,156,606 A
• Filed: 11/17/1998
• Issued: 12/05/2000
• Est. Priority Date: 11/17/1998
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Siemens AG
• Inventors: Michaelis, Alexander
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): Diaz, Jose R
• Application Number:
  US09/193,203
• Time in Patent Office: 749 Days
• Field of Search: 438/243, 438/386, 438/253, 438/239, 438/240
• US Class Current: 438/243
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

A method of forming semiconductor devices in accordance with the present invention includes the steps of providing a deep trench in a substrate, the deep trench having a lower portion and forming a dielectric layer in the deep trench by lining the lower portion of the deep trench with a dielectric layer, the dielectric layer including titanium. A semiconductor device includes a substrate having a trench formed therein, a storage node formed in the trench and capacitively coupled to the substrate and a dielectric layer formed in the trench between the storage node and the substrate, the dielectric layer lining a lower portion of the trench wherein the dielectric layer includes titanium oxide.

Claims

1. A method of forming semiconductor devices comprising the steps of:

providing a deep trench in a substrate, the deep trench having a lower portion; and

forming a dielectric layer in the deep trench by lining the lower portion of the deep trench with the dielectric layer, the dielectric layer including a rutile titanuium dioxide layer.

2. The method as recited in claim 1, further comprising the step of annealing the substrate in a hydrogen ambient environment to remove native oxides from the surface of the substrate, said annealing being performed between the steps of providing said deep trench and forming said dielectric layer.

3. The method as recited in claim 2, further comprising the step of forming a barrier layer in the deep trench prior forming said dielectric layer.

4. The method as recited in claim 3, wherein said step of forming said barrier layer includes the step of exposing said deep trench to an NH₃ ambient environment at a temperature in the range from about 500°

C. to about 700°

C.

5. The method as recited in claim 3, wherein the barrier layer is less than about 1 nanometer in thickness.

6. The method as recited in claim 1, wherein the rutile titanium dioxide layer is formed by depositing a titanium dioxide layer by chemical vapor deposition.

7. The method as recited in claim 6, further comprising the steps of:

oxidizing the titanium dioxide layer; and

annealing the titanium dioxide layer, to obtain a rutile crystal structure.

8. The method as recited in claim 7, further comprising the step of providing a precursor material prior to depositing the rutile titanium dioxide layer.

9. The method as recited in claim 1, wherein the rutile titanium dioxide layer is formed by:

depositing a layer of TiN in the lower portion of the deep trench; and

oxidizing the layer of TiN to form the rutile titanium dioxide layer.

10. The method as recited in claim 9, wherein the step of oxidizing includes the step of oxidizing the layer of TiN by plasma oxidation.

11. The method as recited in claim 9, wherein the step of oxidizing includes the step of oxidizing the layer of TiN by rapid thermal oxidation.

12. A method of forming semiconductor memory devices comprising the steps of:

providing a deep trench in a substrate, the deep trench having a lower portion;

annealing the substrate in a hydrogen environment;

exposing said deep trench to an NH₃ environment to form a first nitride barrier layer;

forming a titanium dioxide rutile dielectric layer in the deep trench;

depositing a second nitride barrier layer over said titanium dioxide rutile dielectric layer;

at least partially filing the deep trench with a conductive filler material thereby forming a storage node; and

removing portions of the titanium dioxide rutile dielectric, first nitride barrier, and second nitride barrier layers such that the titanium dioxide rutile dielectric layer and the first and second nitride barrier layers line the lower portion of the deep trench.

13. The method as recited in claim 12, where said step of forming the rutile layer includes the steps of:

depositing a layer of titanium dioxide in the deep trench;

oxidizing the titanium dioxide layer; and

annealing the titanium dioxide layer to obtain a rutile crystal structure.

14. The method as recited in claim 13, wherein said annealing step is performed at a temperature in the range from about 750°

C. to about 1050°

C.

15. The method as recited in claim 12, wherein said first barrier layer is less than about 1 nanometer in thickness.

16. The method as recited in claim 13, wherein the step of depositing the titanium dioxide layer includes a chemical vapor deposition process.

17. The method as recited in claim 16, further comprising the step of providing a precursor material prior to said step of forming said titanium dioxide rutile dielectric layer.

18. The method as recited in claim 12, wherein the step of forming the titanium dioxide rutile dielectric layer includes the steps of:

depositing a layer of TiN in the deep trench; and

oxidizing the layer of TiN to form rutile (TiO₂).

19. The method as recited in claim 18, wherein the step of oxidizing includes the step of oxidizing the layer of TiN by plasma oxidation.

20. The method as recited in claim 18, wherein the step of oxidizing includes the step of oxidizing the layer of TiN by rapid thermal oxidation.