Method of fabricating vertical FET with sidewall gate electrode

• US 6,156,611 A
• Filed: 07/20/1998
• Issued: 12/05/2000
• Est. Priority Date: 07/20/1998
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Wang, Yang, Lan, Ellen, Eisenbeiser, Kurt, Huang, Jenn-Hwa
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US09/119,550
• Time in Patent Office: 869 Days
• Field of Search: 438/268, 438/270, 438/271, 438/272, 438/589, 438/590, 438/172, 438/167, 438/571, 438/576, 438/669
• US Class Current: 438/268
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.

Claims

1. A method of fabricating a vertical FET with sidewall gate electrode comprising the steps of:

providing a doped semiconductor substrate with a semiconductor drift layer formed thereon and a semiconductor contact layer formed on the semiconductor drift layer;

etching through the semiconductor contact layer into the semiconductor drift layer to form a plurality of parallel, spaced apart elongated mesas, each mesa having an end and an upper surface and each adjacent pair of mesas defining therebetween an elongated trench with substantially vertical sidewalls and a bottom, and defining a gate feed region adjacent the ends of the mesas;

conformally depositing a conductive layer over the plurality of mesas and the trenches, including the sidewalls and the bottoms of the trenches;

depositing a layer of resist over the conductive layer;

removing a portion of the resist to expose portions of the conductive layer on the upper surface of the mesas and the sidewalls and the bottoms of the trenches;

anisotropically etching the conductive layer to remove the exposed portions of the conductive layer on the upper surface of the mesas and the bottoms of the trenches so as to leave portions of the conductive layer on the sidewalls of the trenches;

removing remaining portions of the resist in the gate feed region;

depositing conductive material on the upper surfaces of the mesas and in the gate feed region, and depositing conductive material to connect the portions of the conductive layer on the sidewalls of the trenches to portions of the conductive material in the gate feed region; and

depositing conductive material on a reverse side of the substrate.

2. A method of fabricating a vertical FET with sidewall gate electrode as claimed in claim 1 wherein the step of providing the doped semiconductor substrate with the semiconductor drift layer formed thereon and the semiconductor contact layer formed on the semiconductor drift layer includes epitaxially growing the semiconductor drift layer on the substrate and epitaxially growing the semiconductor contact layer on the semiconductor drift layer.

3. A method of fabricating a vertical FET with sidewall gate electrode as claimed in claim 2 wherein the step of providing the semiconductor doped substrate with the semiconductor drift layer formed thereon and the semiconductor contact layer formed on the semiconductor drift layer includes providing a n+ doped semiconductor substrate, a n doped semiconductor drift layer, and a n+ doped semiconductor contact layer.

4. A method of fabricating a vertical FET with sidewall gate electrode as claimed in claim 1 wherein the step of etching through the semiconductor contact layer into the semiconductor drift layer to form the plurality of mesas includes forming a resist pattern on the semiconductor contact layer and etching with a directional reactive ion etch.

5. A method of fabricating a vertical FET with sidewall gate electrode as claimed in claim 1 wherein the step of conformally depositing the conductive layer includes depositing conductive material for forming Schottky contacts with the drift layer.

6. A method of fabricating a vertical FET with sidewall gate electrode as claimed in claim 5 wherein the step of conformally depositing conductive material for forming Schottky contacts with the drift layer includes conformally depositing TiWN.

7. A method of fabricating a vertical FET with sidewall gate electrode as claimed in claim 5 wherein the step of removing a portion of the resist includes performing a reactive ion etch.

8. A method of fabricating a vertical FET with a sidewall gate electrode as claimed in claim 1 wherein the step of providing the substrate includes providing a compound semiconductor substrate.