Retardation layer for preventing diffusion of metal layer and fabrication method thereof

• US 6,156,655 A
• Filed: 09/30/1999
• Issued: 12/05/2000
• Est. Priority Date: 09/30/1999
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation, United Semiconductor Corp. (United Microelectronics Corporation)
• Inventors: Yeh, Chi-Chin, Huang, Ming-Ching, Ho, Kuai-Jung, Chen, Chih-Rong, Huang, Wen-Yuan
• Primary Examiner(s): Booth, Richard
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/408,612
• Time in Patent Office: 432 Days
• Field of Search: 438/687, 438/637, 438/638, 438/643, 438/647, 438/653, 438/657, 438/666, 438/672
• US Class Current: 438/687
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the conventional barrier layer with a porous layer, wherein the porous layer can be formed either above or below the barrier layer to improve the retardation of the copper atom diffusion. Preferably, the porous layer is formed above the barrier layer.

Claims

1. A fabrication method for a retardation layer which prevents copper diffusion, applicable to a semiconductor process, comprising steps of:

providing a substrate with a first metal line formed thereon;

depositing a dielectric layer on the substrate to cover the first metal line;

forming an opening in the dielectric layer;

forming a first laminated layer to cover a profile of the opening and the dielectric layer, wherein the first laminated layer is conformal to the profile of the opening;

forming a copper layer on the laminated layer for filling the opening;

removing the copper layer and the laminated layer outside the opening so as to form a copper damascene;

forming a second laminated layer to completely cover the copper layer and the dielectric layer.

2. The fabrication method of claim 1, wherein the laminated layer includes a porous layer and a barrier layer.

3. The fabrication method of claim 2, wherein the porous, layer includes a porous silicon layer.

4. The fabrication method of claim 3, wherein the method for forming the porous silicon layer comprising steps of:

forming a polysilicon layer; and

etching the polysilicon layer for forming the porous silicon layer.

5. The fabrication method of claim 2, wherein the porous layer is formed between the copper line and the barrier layer.

6. The fabrication method of claim 2, wherein the barrier layer is formed between the copper line and the porous layer.

7. The fabrication method of claim 1, wherein the copper line includes a copper damascene.

8. The fabrication method of claim 1, wherein the dielectric layer includes a inter-metal dielectric layer.